Semiconductor chip, memory chip, semiconductor package and memory system

• US 9,286,950 B2
• Filed: 05/02/2012
• Issued: 03/15/2016
• Est. Priority Date: 05/03/2011
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Kim, Boseong
• Primary Examiner(s): LE, TOAN K
• Application Number:
  US13/462,321
• Publication Number:
  US 20120281449A1
• Time in Patent Office: 1,413 Days
• Field of Search: 365/63, 365/51, 257/690, 257/686, 257/777
• US Class Current: 1/1
• CPC Class Codes: G11C 11/16 using elements in which the storage effect is based on magnetic spin effect
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: H01L 2224/48137 the bodies being arranged next to each other, e.g. on a common substrate
• CPC Class Codes: H01L 2224/48145 the bodies being stacked
• CPC Class Codes: H01L 2224/48147 with an intermediate bond, e.g. continuous wire daisy chain
• CPC Class Codes: H01L 2225/06562 at least one device in the stack being rotated or offset
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group

Abstract

A semiconductor chip includes a plurality of signal and power pads; and a plurality of chip selection pads, wherein at least one of the plurality of chip selection pads includes a normal pad and an inverse pad.

Claims

1. A semiconductor package comprising:

first and second memory chips configured to be stacked,

wherein one memory chip of the first and second memory chips comprises a plurality of signal and power pads and a plurality of chip selection pads,

wherein first pads of the chip selection pads are electrically connected to a device external to the one memory chip and second pads of the chip selection pads are electrically isolated from the device.

2. The semiconductor package of claim 1, wherein the chip selection pads include a normal pad and an inverse pad.

3. The semiconductor package of claim 2, wherein the first and second memory chips are stacked in a cascade shape.

4. The semiconductor package of claim 3, wherein one of a first normal pad and a first inverse pad of the first memory chip is connected with a first conduction line and the other one of the first normal pad and the first inverse pad of the first memory chip is floated.

5. The semiconductor package of claim 4, wherein one of a second normal pad and a second inverse pad of the second memory chip is connected with the first conduction line and the other one of the second normal pad and the second inverse pad of the second memory chip is floated.

6. The semiconductor package of claim 4, wherein one of a second normal pad and a second inverse pad of the first memory chip is connected with a second conduction line, different from the first conduction line, and the other one of the second normal pad and the second inverse pad of the first memory chip is floated.

7. The semiconductor package of claim 4, further comprising:

a controller chip configured to control the first and second memory chips,

wherein the controller chip comprises a plurality of second signal and power pads corresponding to the plurality of signal and power pads; and

a plurality of control chip selection pads,

wherein the first conduction line is connected with one of the plurality of control chip selection pads.

8. The semiconductor package of claim 7, wherein the controller chip is configured to select one of the first and second memory chips by controlling output signals of the plurality of control chip selection pads.

9. The semiconductor package of claim 4, further comprising:

a plurality of signal and power input and output nodes corresponding to the plurality of signal and power pads; and

a plurality of chip selection nodes,

wherein the first conduction line is connected with one of the plurality of chip selection nodes.

10. The semiconductor package of claim 9, wherein the plurality of chip selection nodes include a plurality of pins or a plurality of solder balls.

11. The semiconductor package of claim 1, wherein the first and second memory chips are stacked in a vertical pillar shape.

12. The semiconductor package of claim 11, further comprising:

a controller chip configured to control the first and second memory chips,

wherein the controller chip comprises a plurality of second signal and power pads corresponding to the plurality of signal and power pads; and

a plurality of control chip selection pads, at least one of the plurality of control chip selection pads corresponds with the plurality of chip selection pads.

13. The semiconductor package of claim 12, wherein one of the first pads of the first memory chip is electrically connected with a first control chip selection pad of the plurality of control chip selection pads.

14. The semiconductor package of claim 13, wherein one of the first pads of the second memory chip is electrically connected with the first control chip selection pad.

15. The semiconductor package of claim 13, wherein another one of the first pads of the first memory chip is electrically connected with a second control chip selection pad, different from the first control chip selection pad, of the plurality of control chip selection pads.

16. The semiconductor package of claim 11, further comprising:

a plurality of signal and power input and output nodes corresponding to the plurality of signal and power pads; and

a plurality of chip selection nodes, at least one of the plurality of chip selection nodes corresponds with the plurality of chip selection pads.

17. The semiconductor package of claim 16, wherein one of the first pads of the first memory chip is electrically connected with a first chip selection node of the plurality of chip selection nodes.

18. The semiconductor package of claim 17, wherein one of the first pads of the second memory chip is electrically connected with the first chip selection node.

19. The semiconductor package of claim 17, wherein another one of the first pads of the first memory chip is electrically connected with a second chip selection node, different from the first chip selection node, of the plurality of chip selection nodes.

20. The semiconductor package of claim 1, wherein the first and second memory chips are stacked in a cascade shape.

21. The semiconductor package of claim 20, wherein a first part of first pads of the first and second memory chips are connected in common with a first conduction line and a second part of the first pads are connected in common with a second conduction line.

22. The semiconductor package of claim 1, wherein the first memory chip comprises:

a plurality of chip selection solder bumps;

a plurality of through silicon vias electrically connected with the plurality of chip selection solder bumps and the plurality of chip selection pads of the first memory chip; and

first and second fuses electrically connected with a through silicon via of the plurality of through silicon vias.

23. The semiconductor package of claim 22, wherein the second memory chip has a same structure as the first memory chip,

wherein chip selection solder bumps of the second memory chip are connected with the chip selection pads of the first memory chip.

24. The semiconductor package of claim 22, wherein one of the first and second fuses connected with the through silicon via of the first memory chip is cut and the other one of the first and second fuses maintains an electric connection state.

25. A semiconductor package comprising:

a plurality of memory chips configured to be stacked; and

a controller chip configured to control the plurality of memory chips,

wherein one memory chip of the first and second memory chips comprises a plurality of signal and power pads and a plurality of chip selection pads,

wherein the controller chip comprises a plurality of control chip selection pads, a first control chip selection pad of the plurality of control chip selection pads is connected with first chip selection pads of first memory chips of the plurality of memory chips, and a second control chip selection pad of the plurality of control chip selection pads is connected with second chip selection pads of second memory chips, different from the first memory chips, of the plurality of memory chips.

26. The semiconductor package of claim 25, wherein the first control chip selection pads are connected with the first chip selection pads in common through a first conduction line.

27. The semiconductor package of claim 25, wherein the second control chip selection pads are connected with the second chip selection pads in common through a second conduction line.

28. The semiconductor package of claim 25, wherein

a third control chip selection pad of the plurality of control chip selection pads is connected with third chip selection pads of third memory chips of the plurality of memory chips,

wherein a first part of the third memory chips are overlapped with the first memory chips and a second part of the third memory chips are overlapped with the second memory chips.

29. The semiconductor package of claim 28,

wherein a fourth control chip selection pad of the plurality of control chip selection pads is connected with fourth chip selection pads of fourth memory chips, different from the third memory chips, of the plurality of memory chips,

wherein a third part of the fourth memory chips are overlapped with the first memory chips and a fourth part of the fourth memory chips are overlapped with the second memory chips.

30. The semiconductor package of claim 25, wherein the first control chip selection pad is a normal pad and the second control chip selection pad is an inverse pad, the normal pad and the inverse pad forming a differential pair.

31. The semiconductor package of claim 30, wherein the normal pad and the inverse pad are connected with different memory chips each other.

32. A semiconductor package comprising:

a controller chip configured to control a memory;

a plurality of signal and power nodes electrically connected with a plurality of signal and power pads of the controller chip; and

a plurality of chip selection nodes electrically connected with a plurality of chip selection pads of the controller chip,

wherein a chip selection pad of the plurality of chip selection nodes comprises a normal pad and an inverse pad, and

wherein the chip selection node of the plurality of chip selection nodes comprises the normal node and the inverse node, at least one of the normal node and the inverse node is connected with the normal pad and the inverse pad.

33. A memory controller chip comprising:

a plurality of signal and power pads; and

a plurality of chip selection pads including a normal pad and an inverse pad, the normal pad and the inverse pad being a differential pair,

wherein the chip selection pads are independently controlled to have a logically high or a logically low value, and

wherein a combination of the chip selection pads is output as a chip selection signal.

34. A memory system comprising:

first and second memory chips configured to be stacked; and

a memory controller chip configured to control the first and second memory chips,

wherein one of the first and second memory chips is configured to communicate with the memory controller chip via a plurality of signal and power pads and a plurality of chip selection pads,

wherein one of the first and second memory chips and the memory controller chip includes a normal chip selection pad and an inverse chip selection pad.

35. The memory system of claim 34, wherein the first and second memory chips and the memory controller chip constitute a memory card.

36. The memory system of claim 34, wherein the first and second memory chips and the memory controller chip constitute a solid state drive.

37. The memory system of claim 34, wherein the first and second memory chips and the memory controller chip form a single package.

38. The memory system of claim 34, wherein the first and second memory chips form a memory package and the memory controller chip forms a controller package.

39. A solid state drive comprising:

a substrate;

a plurality of memory packages;

a controller package; and

a connector,

wherein at least one of the plurality of memory packages comprises first and second memory chips, the first and second memory chips are configured to be stacked, and

wherein the controller package comprises a controller chip, the controller chip configured to select the at least one of the plurality of memory packages using a smaller number of signals than a total number of signals of the at least one of the plurality of memory packages.

40. The solid state drive of claim 39, wherein at least one of the plurality of memory packages and the controller package communicates with an external device via the connector.