Controlling pass voltages to minimize program disturb in charge-trapping memory

• US 9,286,987 B1
• Filed: 09/09/2014
• Issued: 03/15/2016
• Est. Priority Date: 09/09/2014
• Status: Active Grant

• Current Assignee: SanDisk Technologies LLC (Western Digital Corporation)
• Original Assignee: Sandisk Technologies Incorporated (Western Digital Corporation)
• Inventors: Dong, Yingda, Chen, Hong-Yan
• Primary Examiner(s): Nguyen, Viet Q
• Application Number:
  US14/481,304
• Publication Number:
  US 20160071595A1
• Time in Patent Office: 553 Days
• Field of Search: 365/185.17, 365/185.18, 365/185.19, 365/185.22
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/0466 comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS] G11C16/0483, G11C16/0491 take precedence
• CPC Class Codes: G11C 16/0483 comprising cells having several storage transistors connected in series
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/3427 Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
• CPC Class Codes: G11C 16/3459 Circuits or methods to verify correct programming of nonvolatile memory cells

Abstract

Techniques are provided for preventing program disturb of unselected memory cells during programming of a selected memory cell in a NAND string which includes a continuous charge-trapping layer, either in a two-dimensional or three-dimensional configuration. In such a NAND string, regions between the memory cells can be inadvertently programmed as parasitic cells due to the program voltage and pass voltages on the word lines. For programmed cells, an upshift in threshold voltage due to a parasitic cell can be avoided by providing a higher pass voltage on an adjacent later-programmed word line than on an adjacent previously-programmed word line. For erased cells, an upshift in threshold voltage due to the parasitic cells can be reduced by progressively lowering the pass voltage on the adjacent later-programmed word line. The lowering can occur when memory cells of a lowest target data state complete programming.

Claims

1. A method for programming in a memory device, comprising:

programming selected memory cells connected to a selected word line of a set of word lines, the selected memory cells are programmed to a plurality of target data states, and memory cells which are to remain in an erased state are also connected to the selected word line, the programming is performed by performing a plurality of program-verify iterations for the selected word line, each program-verify iteration of the plurality of program-verify iterations is performed by applying a program voltage followed by performing a verify test for one or more target data states of the plurality of target data states, and the program voltage is stepped up in the plurality of program-verify iterations; and

during each program voltage, applying a first pass voltage to a word line in the set of word lines which is adjacent to the selected word line and after the selected word line in a word line programming order, while applying a second pass voltage to a word line in the set of word lines which is adjacent to the selected word line and before the selected word line in a word line programming order, wherein during one or more initial program-verify iterations of the plurality of program-verify iterations, the first pass voltage exceeds the second pass voltage by a difference, the first pass voltage becomes progressively smaller during subsequent program-verify iterations of the plurality of program-verify iterations, and the difference becomes progressively smaller during the subsequent program-verify iterations.

2. The method of claim 1, wherein:

the difference by which the first pass voltage exceeds the second pass voltage is at least as high as a difference between a verify voltage of a highest target data state of the plurality of target data states and a verify voltage of a lowest target data state of the plurality of target data states.

3. The method of claim 1, wherein:

the subsequent program-verify iterations comprise program-verify iterations in which the first pass voltage is fixed at a first reduced level followed by program-verify iterations in which the first pass voltage is fixed at a second reduced level, below the first reduced level.

4. The method of claim 1, wherein:

the first pass voltage and the difference start to become progressively smaller when a determination is made that a specified portion of memory cells which are to be programmed to a lowest target data state of the plurality of target data states have passed a verify test.

5. The method of claim 1, wherein:

the first pass voltage and the difference start to become progressively smaller after a predetermined number of program-verify iterations of the plurality of program-verify iterations have been performed.

6. The method of claim 1, further comprising:

determining a programming progress of the selected memory cells, wherein the first pass voltage and the difference start to become progressively smaller based on the programming progress.

7. The method of claim 1, further comprising:

determining a programming progress of the selected memory cells; and

deciding when to keep the first pass voltage at a fixed minimum for a remainder of the plurality of program-verify iterations based on the programming progress, wherein the first pass voltage becomes progressively smaller until it reaches the fixed minimum.

8. The method of claim 1, wherein:

the first pass voltage and the difference are fixed during the one or more initial program-verify iterations.

9. The method of claim 1, wherein:

the first pass voltage is equal to the second pass voltage in a final program-verify iteration of the plurality of program-verify iterations.

10. The method of claim 1, wherein:

the second pass voltage becomes progressively smaller during the subsequent program-verify iterations of the plurality of program-verify iterations.

11. The method of claim 1, wherein:

the second pass voltage becomes progressively larger during the subsequent program-verify iterations of the plurality of program-verify iterations.

12. The method of claim 1, wherein:

memory cells connected to the set of word lines are arranged in NAND strings; and

each NAND string comprises a charge-trapping layer which extends continuously in the NAND string.

13. A memory device, comprising:

selected memory cells connected to a selected word line of a set of word lines; and

a control circuit, the control circuit;

is configured to program the selected memory cells to a plurality of target data states, wherein memory cells which are to remain in an erased state are also connected to the selected word line;

to perform the programming, is configured to perform a plurality of program- verify iterations for the selected word line;

to perform each program-verify iteration of the plurality of program-verify iterations, is configured to apply a program voltage followed by performing a verify test for one or more target data states of the plurality of target data states, wherein the program voltage is stepped up in the plurality of program-verify iterations; and

during each program voltage, is configured to apply a first pass voltage to a word line in the set of word lines which is adjacent to the selected word line and after the selected word line in a word line programming order, while applying a second pass voltage to a word line in the set of word lines which is adjacent to the selected word line and before the selected word line in a word line programming order, wherein during one or more initial program-verify iterations of the plurality of program-verify iterations, the first pass voltage exceeds the second pass voltage by a difference, the first pass voltage becomes progressively smaller during subsequent program-verify iterations of the plurality of program-verify iterations, and the difference becomes progressively smaller during the subsequent program-verify iterations.