Multi-chip non-volatile semiconductor memory package including heater and sensor elements

• US 9,286,991 B1
• Filed: 03/05/2015
• Issued: 03/15/2016
• Est. Priority Date: 02/17/2015
• Status: Active Grant

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Darryl G. Walker
• Inventors: Walker, Darryl G.
• Primary Examiner(s): Yoha, Connie
• Application Number:
  US14/639,325
• Time in Patent Office: 376 Days
• Field of Search: 365/185.05, 365/185.24, 365/185.29
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2856 Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM]
• CPC Class Codes: G11C 16/04 using variable threshold transistors, e.g. FAMOS
• CPC Class Codes: G11C 16/06 Auxiliary circuits, e.g. for writing into memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/26 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 16/28 using differential sensing or reference cells, e.g. dummy cells
• CPC Class Codes: G11C 16/349 Arrangements for evaluating degradation, retention or wearout, e.g. by counting erase cycles
• CPC Class Codes: G11C 29/4401 for self repair
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring
• CPC Class Codes: G11C 7/04 with means for avoiding disturbances due to temperature effects
• CPC Class Codes: H01L 21/324 Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering H01L21/20 - H01L21/288 and H01L21/302 - H01L21/322 take precedence
• CPC Class Codes: H01L 22/10 Measuring as part of the manufacturing process burn-in G01R31/2855
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/34 Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/345 Arrangements for heating thermal treatment apparatus H01L21/00
• CPC Class Codes: H01L 23/36 Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks H01L23/28, H01L23/40, H01L23/42, H01L23/44, H01L23/46 take precedence; heating H01L23/345
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H05B 3/146 : Conductive polymers, e.g. polyethylene, thermoplastics
• CPC Class Codes: H05B 3/148 : Silicon, e.g. silicon carbide, magnesium silicide, heating transistors or diodes
• CPC Class Codes: H10B 41/30 : characterised by the memory core region
• CPC Class Codes: H10B 69/00 : Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A method of healing a plurality of non-volatile semiconductor memory devices on a multi-chip package is disclosed. The multi-chip package can be heated to a temperature range having a temperature range upper limit value and a temperature range lower limit value. The temperature of the multi-chip package can be kept essentially within the temperature range for a predetermined time period by monitoring a thermal sensing element with a sensing circuit outside of the multi-chip package. The thermal sensing element may be located near the components with the lowest failure temperature to ensure the multi-chip package is not damaged during the healing process.

Claims

1. A system, comprising:

a chip package including

a first semiconductor device;

a thermal sensing element having a first thermal sensing element terminal and a second thermal sensing element terminal;

a plurality of connections formed on the bottom surface of the package wherein a first one of the plurality of connections is electrically connected to the first thermal sensing element terminal and a second one of the plurality of connections is electrically connected to the second thermal sensing element; and

a sensor circuit having a first sense node coupled to the first one of the plurality of connections and a second sense node coupled to the second one of the plurality of connections wherein

the sensor circuit is coupled to receive a sensor enable signal and provide a temperature range upper limit detect signal having a logic level determined by the temperature of the thermal sensing element when the sensor enable signal has an enable logic level wherein

the sensor circuit includes a first amplifier circuit, the first amplifier circuit having a first input terminal coupled to the second sense node, the first amplifier circuit is coupled to provide the temperature range upper limit detect signal at a first amplifier circuit output terminal.

2. The system of claim 1, wherein:

the sensor circuit is included on a third semiconductor device outside the chip package.

3. The system of claim 1, further including the step of:

the first amplifier circuit has a second input terminal coupled to a first reference potential.

4. The system of claim 3, wherein:

the first reference potential is generated from a first resistor and a second resistor coupled in series to form a first voltage divider that provides the first reference potential at a first voltage divider node.

5. The system of claim 3, wherein:

the sensor circuit provides a temperature range lower limit detect signal having a logic level determined by the temperature of the thermal sensing element.

6. The system of claim 3, further including the step of:

the sensor circuit includes a second amplifier circuit having a first input terminal coupled to the second sense node, the second amplifier circuit is coupled to provide the temperature range lower limit detect signal at a second amplifier circuit output terminal.

7. The system of claim 6, further including the step of:

the second amplifier circuit has a second input terminal coupled to a second reference potential.

8. The system of claim 7, wherein:

the second reference potential is generated from a third resistor and a fourth resistor coupled in series to form a second voltage divider that provides the second reference potential at a second voltage divider node.

9. The system of claim 8, wherein:

the sensor circuit further includes a fifth resistor coupled between the second sense node and a third reference potential.

10. The system of claim 4, wherein:

the sensor circuit further includes an insulated gate field effect transistor (IGFET) having a source terminal coupled to a power supply potential, a drain terminal coupled to a first terminal of the first resistor and a gate terminal coupled to receive the sensor enable signal.

11. The system of claim 1, wherein:

the thermal sensing element is intervening the first semiconductor device and the plurality of connections.

12. The system of claim 11, wherein:

the chip package further includes a second semiconductor device on an upper surface of the first semiconductor device.

13. The system of claim 12, wherein:

the first and second semiconductor devices are non-volatile semiconductor memory devices.

14. The system of claim 1, wherein:

the chip package further includes a heater element having a first heater element terminal electrically connected to a third one of the plurality of connections, the heater element providing heat to the chip package in response to a heater drive signal received at the third one of the plurality of connections.

15. The system of claim 1, wherein:

the plurality of connection are a plurality of solder ball connections forming a grid array.

16. The system of claim 1, wherein:

the first semiconductor device is a non-volatile semiconductor memory device.

17. The system of claim 1, wherein:

the thermal sensing element comprising a material selected from the group consisting of;

silver and platinum.

18. The system of claim 1, wherein:

the thermal sensing element comprising copper.

19. The system of claim 1, wherein:

the thermal sensing element comprising aluminum.

20. The system of claim 1, wherein:

the thermal sensing element comprising tungsten.