Sidewall image transfer process for fin patterning

• US 9,287,135 B1
• Filed: 05/26/2015
• Issued: 03/15/2016
• Est. Priority Date: 05/26/2015
• Status: Active Grant

• Current Assignee: Tessera, Inc. (Adeia Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Doris, Bruce B., He, Hong, Kanakasabapathy, Sivananda K., Reznicek, Alexander
• Primary Examiner(s): Movva, Amar
• Assistant Examiner(s): Maruf, Sheikh
• Application Number:
  US14/721,430
• Time in Patent Office: 294 Days
• Field of Search: 438696-706, 438/736, 438/717, 257/401, 257/618, 257632-637, 257/288, 257/E21.235, 257/E21.24
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02164 the material being a silicon oxide, e.g. SiO2
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/02274 in the presence of a plasma [PECVD]
• CPC Class Codes: H01L 21/0228 deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/3086 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/3212 by chemical mechanical polishing [CMP]
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A method of using sidewall image transfer (SIT) process to pattern fin structures is provided. The method includes providing a fin-patterning substrate containing a first hard-mask layer and a second hard-mask layer over a semiconductor substrate. Trench openings formed on the semiconductor substrate extending vertically through the first hard-mask layer and the second hard-mask layer. Trench openings are filled with a third hard-mask material. The second hard-mask layer is removed to reveal hard-mask mandrels. First sidewall spacers are formed on the opposite sides of the hard-mask mandrels using atomic layer deposition (ALD) process. The semiconductor substrate is etched using the first sidewall spacers and the hard-mask mandrels as mask, subsequently the spacers, the mandrels and the hard-mask layer are removed to reveal fin structures. The method of the present invention is to form fins at a very tight fin pitch by using the very tight thickness controllability of ALD process. By repeating the ALD step twice or more to form multiple SIT spacers the fin pitch size can be reduced further. The inventive method is suitable for fabricating tight fin pitch to less than about 20 nm.

Claims

1. A method for fin patterning comprising:

providing a fin-patterning substrate comprising a first hard-mask layer and a second hard-mask layer over a semiconductor substrate, wherein the second hard-mask layer is on top of the first hard-mask layer;

forming a plurality of trench openings on the semiconductor substrate extending vertically through the first hard-mask layer and the second hard-mask layer;

filling the plurality of trench openings with a third hard-mask material to form a plurality of hard-mask mandrels;

removing the second hard-mask layer to reveal the plurality of hard-mask mandrels protruding above the first hard-mask layer over the semiconductor substrate;

forming a layer of first spacer material covering top of the first hard-mask layer under openings which are formed after the removing the second hard-mask layer, and covering top and sides of the plurality of hard-mask mandrels;

removing first spacer material from the top of the first hard-mask layer and the top of the hard-mask mandrels, and from sides on two line ends of each hard-mask mandrel to form a plurality of first sidewall spacers;

etching through the first hard-mask layer under openings, which are located directly on top of the first hard-mask layer and are on areas where the first spacer material is removed, into the semiconductor substrate to form fin structures under the first sidewall spacers; and

removing the plurality of hard-mask mandrels, the plurality of first sidewall spacers and the first hard-mask layer to reveal the fin structures.

2. The method of claim 1, wherein forming a plurality of trench openings on the semiconductor substrate comprises:

forming a patterned resist on the second hard-mask layer, wherein the patterned resist contains a trench pattern; and

transferring the trench pattern from the patterned resist to the semiconductor substrate by etching through the first and second hard-mask layer to the semiconductor substrate to form the plurality of trench openings.

3. The method of claim 1, wherein material of the first hard-mask layer is silicon oxide.

4. The method of claim 1, wherein filling the plurality of trench openings with a third hard-mask material to form a plurality of hard-mask mandrels comprises:

performing high-density plasma chemical vapor deposition (HDPCVD) or atmospheric pressure chemical vapor deposition (APCVD) to fill the plurality of trench openings with HDPCVD oxide or APCVD oxide; and

performing a planarization process with chemical mechanical polishing (CMP) to remove the HDPCVD oxide or the APCVD oxide atop of the second hard-mask layer.

5. The method of claim 1, wherein material of the second hard-mask layer is silicon nitride.

6. The method of claim 1, wherein removing the second hard-mask layer to reveal the plurality of hard-mask mandrels comprises:

exposing the fin-patterning substrate to a chemical solution, wherein the chemical solution comprises a sulfuric acid component and a hydrogen peroxide component.

7. The method of claim 1, wherein forming a layer of first spacer material comprises:

conformally depositing the first spacer material onto the fin-patterning substrate using atomic layer deposition (ALD).

8. The method of claim 1, wherein the first spacer material is silicon nitride.

9. The method of claim 1, wherein removing first spacer material from sides on two line ends of each hard-mask mandrel comprises:

orienting each side of the two line ends to have a non orthogonal tilt angle between a path of an ion beam and surface of the side during a reactive ion etching process.

10. The method of claim 1, wherein removing the plurality of hard-mask mandrels, the plurality of first sidewall spacers and the first hard-mask layer comprises:

exposing the fin-patterning substrate to an oxide removal agent which includes hydrogen fluoride in an aqueous solution in a range of approximately 5;

1 to 20,000;

1 (water;

hydrogen fluoride).

11. A method for fin patterning comprising:

providing a fin-patterning substrate comprising a first hard-mask layer and a second hard-mask layer over a semiconductor substrate, wherein the second hard-mask layer is on top of the first hard-mask layer;

forming a plurality of trench openings on the semiconductor substrate extending vertically through the first hard-mask layer and the second hard-mask layer;

filling the plurality of trench openings with a third hard-mask material to form a plurality of hard-mask mandrels;

removing the second hard-mask layer to reveal the plurality of hard-mask mandrels protruding above the first hard-mask layer over the semiconductor substrate;

forming a layer of first spacer material covering top of the first hard-mask layer under openings which are formed after the removing the second hard-mask layer, and covering top and sides of the plurality of hard-mask mandrels;

removing first spacer material from the top of the first hard-mask layer and the top of the hard-mask mandrels, and from sides on two line ends of each hard-mask mandrel to form a plurality of first sidewall spacers;

forming a layer of second spacer material covering all tops and sides adjacent to air of the first hard-mask layer, the plurality of hard-mask mandrels, and the plurality of first sidewall spacers;

removing second spacer material from the tops and sides of the first hard-mask layer, the plurality of hard-mask mandrels, and the plurality of first sidewall spacers, except two opposite sidewalls of each of the first sidewall spacers to form a plurality of second sidewall spacers;

forming third spacers with a third spacer material directly on top of the first hard-mask layer under openings which are formed after the removing second spacer material;

removing the plurality of second sidewall spacers;

etching through the first hard-mask layer under openings, which are located directly on top of the first hard-mask layer and are on areas where the second sidewall spacers are removed, into the semiconductor substrate to form fin structures under the first sidewall spacers and the third spacers; and

removing the plurality of hard-mask mandrels, the plurality of first sidewall spacers, the third spacers and the first hard-mask layer to reveal the fin structures.

12. The method of claim 11, wherein the third spacer material is same as the first spacer material.

13. The method of claim 11, wherein forming a plurality of trench openings on the semiconductor substrate comprises:

forming a patterned resist on the second hard-mask layer, wherein the patterned resist contains a trench pattern; and

transferring the trench pattern from the patterned resist to the semiconductor substrate by etching through the first and second hard-mask layer to the semiconductor substrate to form the plurality of trench openings.

14. The method of claim 11, wherein material of the first hard-mask layer is silicon oxide.

15. The method of claim 11, wherein filling the plurality of trench openings with a third hard-mask material to form a plurality of hard-mask mandrels comprises:

performing high-density plasma chemical vapor deposition (HDPCVD) or atmospheric pressure chemical vapor deposition (APCVD) to fill the plurality of trench openings with HDPCVD oxide or APCVD oxide; and

performing a planarization process with chemical mechanical polishing (CMP) to remove the HDPCVD oxide or the APCVD oxide atop of the second hard-mask layer.

16. The method of claim 11, wherein forming a layer of first spacer material comprises:

conformally depositing the first spacer material onto the fin-patterning substrate using atomic layer deposition (ALD).

17. The method of claim 11, wherein the first spacer material is silicon nitride.

18. The method of claim 11, wherein the second spacer material is amorphous silicon, amorphous carbon, or amorphous silicon germanium.

19. The method of claim 11, wherein forming a layer of second spacer material comprises:

conformally depositing the second spacer material onto the fin-patterning substrate using atomic layer deposition (ALD).

20. The method of claim 11, wherein the fin structures has a fin pitch less than about 20 nm.