Barrier for through-silicon via

• US 9,287,166 B2
• Filed: 02/26/2014
• Issued: 03/15/2016
• Est. Priority Date: 03/23/2009
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chiou, Wen-Chih, Wu, Weng-Jin
• Primary Examiner(s): Nguyen, Dao H
• Application Number:
  US14/191,137
• Publication Number:
  US 20140175652A1
• Time in Patent Office: 748 Days
• Field of Search: 438/618, 438/627, 438/653, 438/656, 438/708, 257/737, 257/741, 257/751, 257/763, 257/E21.171, 257/E21.175, 257/E21.575, 257/E21.584
• US Class Current: 1/1
• CPC Class Codes: H01L 21/76846 Layer combinations
• CPC Class Codes: H01L 21/76847 the layer being positioned within the main fill metal
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2224/05552 in top view
• CPC Class Codes: H01L 2224/0557 the external layer being disposed on a via connection of the semiconductor or solid-state body
• CPC Class Codes: H01L 23/5226 Via connections in a multilevel interconnection structure
• CPC Class Codes: H01L 24/05 of an individual bonding area
• CPC Class Codes: H01L 24/06 of a plurality of bonding areas
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/01019 Potassium [K]
• CPC Class Codes: H01L 2924/01025 Manganese [Mn]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/04941 TiN
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/19041 being a capacitor
• CPC Class Codes: H01L 2924/19042 being an inductor
• CPC Class Codes: H01L 2924/19043 being a resistor

Abstract

A system and a method for protecting vias is disclosed. An embodiment comprises forming an opening in a substrate. A barrier layer disposed in the opening including along the sidewalls of the opening. The barrier layer may include a metal component and an alloying material. A conductive material is formed on the barrier layer and fills the opening. The conductive material to form a via (e.g., TSV).

Claims

1. A method comprising:

forming on a first surface of a semiconductor substrate an integrated circuit device;

forming over the first surface a dielectric layer;

etching an opening through the dielectric layer and at least partially through the substrate, the opening having sidewalls;

conformally forming a barrier layer on the sidewalls, wherein the barrier layer includes a composition having a metal component and a carbon alloying material at a concentration of no greater than about 15% of the barrier layer; and

forming a conductor on the barrier layer, wherein the conductor completely fills the opening, the conductor having a top surface coplanar with a top surface of the dielectric layer and a bottom surface at a bottom surface of the opening proximate a second surface of the substrate.

2. The method of claim 1, further comprising:

thinning the substrate from a second side until the bottom surface of the conductor is exposed; and

forming a contact electrically connected to the conductor.

3. The method of claim 2, further comprising forming a passivation layer at least partially over the contact, and wherein the contact electrically couples the integrated circuit to an circuit external to the integrated circuit.

4. The method of claim 1, wherein conformally forming a barrier layer on the sidewalls comprises:

depositing a single atomic layer of barrier material; and

repeating the step of depositing a single atomic layer of barrier material until a desired thickness of barrier material has been reached.

5. The method of claim 1, wherein conformally forming a barrier layer comprises forming a barrier layer having a variation in thickness across its entire length of less than about 20% variation.

6. The method of claim 1, wherein conformally forming a barrier layer comprises depositing barrier material using a process selected from the group consisting of atomic layer deposition, plasma enhanced chemical vapor deposition, and plasma enhanced physical vapor deposition.

7. The method of claim 1, further comprising forming the barrier layer on a bottom of the opening and wherein the barrier layer has a thickness on the sidewalls that is substantially equal to the thickness on the bottom of the opening, when formed.

8. The method of claim 1, further comprising:

forming a dielectric liner on the sidewalls before conformally forming a barrier layer on the sidewalls.

9. The method of claim 1, further comprising forming an adhesion layer on the barrier layer before forming the conductor.

10. A method comprising:

forming at least one active device on a first surface of a semiconductor substrate;

forming an interlevel dielectric layer (ILD) over the first surface and the at least one active device;

forming a contact structure extending through the ILD and electrically contacting the at least one active device;

etching an opening extending through the ILD and at least partially through the semiconductor substrate, the opening having sidewalls and a bottom, wherein a portion of the sidewalls in the ILD are substantially aligned with a portion of the sidewalls in the semiconductor substrate;

forming a liner on the ILD and on the sidewalls and bottom of the opening;

forming a

barrier layer on the liner by depositing barrier material using a precursor composition having a metal component and a carbon alloying material, the carbon alloying material having a concentration of no greater than about 15% of the barrier material;

forming an adhesion layer on the barrier layer;

forming a seed layer on the adhesion layer and electroplating a conductor on the seed layer and wholly filling the opening;

removing portions of a second surface of the semiconductor substrate to expose the conductor; and

forming an electrical contact on at least one end of the conductor.

11. The method of claim 10, wherein the barrier layer comprises tantalum nitride, tantalum, titanium, titanium nitride or combinations thereof.

12. The method of claim 10, wherein the content of carbon in the barrier layer is less than approximately 5 percent.

13. The method of claim 10, wherein the barrier layer is formed using an atomic layer deposition (ALD).