Method of manufacturing a semiconductor device including through silicon plugs

• US 9,287,440 B2
• Filed: 07/15/2013
• Issued: 03/15/2016
• Est. Priority Date: 04/05/2010
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Yu, Chen-Hua, Chang, Hung-Pin, Lin, Yung-Chi, Yu, Chia-Lin, Hung, Jui-Pin, Hwang, Chien Ling
• Primary Examiner(s): Page, Dale E
• Application Number:
  US13/942,112
• Publication Number:
  US 20130302979A1
• Time in Patent Office: 974 Days
• Field of Search: 257/99
• US Class Current: 1/1
• CPC Class Codes: H01L 21/3065 Plasma etching; Reactive-ion etching
• CPC Class Codes: H01L 21/486 Via connections through the substrate with or without pins
• CPC Class Codes: H01L 21/6835 using temporarily an auxiliary support
• CPC Class Codes: H01L 21/76843 formed in openings in a dielectric
• CPC Class Codes: H01L 21/76876 for deposition from the gas phase, e.g. CVD
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material
• CPC Class Codes: H01L 21/76879 by selective deposition of conductive material in the vias, e.g. selective C.V.D. on semiconductor material, plating plating on semiconductors in general H01L21/288
• CPC Class Codes: H01L 21/76898 formed through a semiconductor substrate
• CPC Class Codes: H01L 2221/68345 used as a support during the manufacture of self supporting substrates
• CPC Class Codes: H01L 2221/68359 used as a support during manufacture of interconnect decals or build up layers
• CPC Class Codes: H01L 2224/16 of an individual bump connector
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/32506 comprising an eutectic alloy
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/48233 connecting the wire to a potential ring of the item
• CPC Class Codes: H01L 2224/49113 the connectors connecting different bonding areas on the semiconductor or solid-state body to a common bonding area outside the body, e.g. converging wires
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 23/147 : Semiconductor insulating substrates semiconductor conductive substrates H01L23/4926
• CPC Class Codes: H01L 23/481 : Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/49827 : Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 24/29 : of an individual layer connector
• CPC Class Codes: H01L 24/48 : of an individual wire connector
• CPC Class Codes: H01L 24/49 : of a plurality of wire connectors
• CPC Class Codes: H01L 24/97 : the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01019 : Potassium [K]
• CPC Class Codes: H01L 2924/01029 : Copper [Cu]
• CPC Class Codes: H01L 2924/01078 : Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01322 : Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/04941 : TiN
• CPC Class Codes: H01L 2924/12041 : LED
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/3512 : Cracking
• CPC Class Codes: H01L 2933/0066 : relating to arrangements for conducting electric current to or from the semiconductor body
• CPC Class Codes: H01L 33/005 : Processes
• CPC Class Codes: H01L 33/0054 : for devices with an active region comprising only group IV elements
• CPC Class Codes: H01L 33/486 : adapted for surface mounting
• CPC Class Codes: H01L 33/62 : Arrangements for conducting electric current to or from the semiconductor body, e.g. lead-frames, wire-bonds or solder balls
• CPC Class Codes: H01L 33/641 : characterized by the materials
• CPC Class Codes: H01L 33/644 : in intimate contact or integrated with parts of the device other than the semiconductor body
• CPC Class Codes: H01L 33/647 : the elements conducting electric current to or from the semiconductor body

Abstract

A method of making a semiconductor device, the method includes forming a first opening and a second opening in a substrate. The method further includes forming a conductive material in the first opening and in the second opening, the conductive material comprising a joined portion where the conductive material in the first opening and the conductive material in the second opening are electrically and thermally connected together at a first surface of the substrate. The method further includes reducing a thickness of the substrate from a second surface of the substrate, opposite the first surface, to expose the conductive material in the first opening and the conductive material in the second opening. The method further includes connecting a device to the second surface of the substrate.

Claims

1. A method of making a semiconductor device, the method comprising:

forming a first opening and a second opening in a top surface of a substrate;

forming a conductive material in the first opening and in the second opening, the conductive material comprising a joined portion of the conductive material extending along the top surface, where the conductive material in the first opening and the conductive material in the second opening are electrically and thermally connected together;

reducing a thickness of the substrate from a second surface of the substrate, opposite the top surface, to expose the conductive material in the first opening and the conductive material in the second opening; and

connecting a device to the second surface of the substrate.

2. The method of claim 1, wherein forming the first opening and the second opening comprises:

forming a dielectric layer over the top surface of the substrate, wherein the dielectric layer has a thickness ranging from about 500 Angstroms (Å

) to about 10,000 Å

;

defining gaps in the dielectric layer; and

etching the first opening and the second opening in the substrate through the defined gaps to a depth ranging from about 20 micrometers (μ

m) to about 200 μ

m, wherein the first opening and the second opening independently have a width ranging from about 5 μ

m to about 100 μ

m.

3. The method of claim 1, further comprising:

forming an isolation layer in the first opening and in the second opening, wherein the isolation layer separates the conductive material from the substrate.

4. The method of claim 3, wherein forming the isolation layer comprises forming an oxide layer or a nitride layer, the isolation layer having a thickness ranging from about 500 Å

to about 15,000 Å

.

5. The method of claim 3, wherein forming the isolation layer further comprises doping the isolation layer.

6. The method of claim 3, further comprising forming a seed layer over the isolation layer, wherein the seed layer separates the isolation layer from the conductive material.

7. The method of claim 1, wherein reducing the thickness of the substrate comprises:

attaching the top surface of the substrate to a second substrate;

grinding the substrate at the second surface of the substrate; and

planarizing the ground second surface of the substrate.

8. The method of claim 1, wherein connecting the device to the second surface of the substrate comprises:

forming a dielectric layer on the second surface of the substrate;

defining gaps in the dielectric layer, wherein the defined gaps overlap with the conductive material.

9. The method of claim 8, wherein connecting the device to the second surface of the substrate further comprises:

forming a metal pad in the defined gaps; and

forming a diffusion barrier layer over the metal pad.

10. The method of claim 9, wherein connecting the device to the second surface of the substrate further comprises eutectically bonding the device to the diffusion barrier layer.

11. The method of claim 1, further comprising forming a phosphorous layer over the device.

12. The method of claim 1, further comprising forming a molding material around the device.

13. The method of claim 1, wherein reducing the thickness of the substrate comprises reducing the thickness of the substrate to a range from about 20 μ

m to about 200 μ

m.

14. A method of making a semiconductor device, the method comprising:

etching a top surface of a substrate to form a first opening and a second opening;

forming an isolation layer in the first opening and the second opening, the isolation layer having a higher thermal resistance than the substrate;

forming a continuous conductive material in both of the first opening and the second opening, wherein the isolation layer is located between conductive material and the substrate;

forming a metal pad over the top surface of the substrate, wherein the metal pad is electrically and thermally connected to the conductive material in the first opening and the conductive material in the second opening; and

bonding a device to the metal pad, wherein the metal pad is electrically and thermally connected to the device.

15. The method of claim 14, wherein etching the substrate to form the first opening and the second opening comprises forming the first opening and the second opening separated by a distance equal to or greater than a diameter of at least one of the first opening or the second opening.

16. The method of claim 14, wherein etching the substrate to form the first opening and the second opening comprises forming the first opening concentric with the second opening.

17. The method of claim 14, wherein etching the substrate to form the first opening and the second opening comprises forming the first opening and the second opening having a double-sided comb shape.

18. The method of claim 14, wherein forming the isolation layer further comprises doping the isolation layer.

19. The method of claim 14, wherein forming the conductive material in the first opening and the second opening comprises electrically and thermally connecting the conductive material in the first opening and the second opening.

20. The method of claim 14, further comprising:

etching the substrate to form a third opening in the substrate;

forming the conductive material in the third opening, wherein the conductive material in the third opening is electrically and thermally isolated from the conductive material in the first opening and the conductive material in the second opening.