Core module for wireless sensing system

• US 9,287,737 B2
• Filed: 05/29/2013
• Issued: 03/15/2016
• Est. Priority Date: 02/18/2013
• Status: Active Grant

• Current Assignee: Shuenn Yuh Lee
• Original Assignee: Shuenn-Yuh Lee
• Inventors: Lee, Shuenn-Yuh, Wang, Cheng-Pin
• Primary Examiner(s): Fureman, Jared
• Assistant Examiner(s): Bukhari, Aqeel
• Application Number:
  US13/904,026
• Publication Number:
  US 20140232207A1
• Time in Patent Office: 1,021 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: H02J 50/20 using microwaves or radio frequency waves
• CPC Class Codes: H02J 50/80 involving the exchange of data, concerning supply or distribution of electric power, between transmitting devices and receiving devices
• CPC Class Codes: H04B 5/72 for local intradevice communication
• CPC Class Codes: H04B 5/73 for taking measurements, e.g. using sensing coils
• CPC Class Codes: H04B 5/77 for interrogation
• CPC Class Codes: H04B 5/79 for data transfer in combination with power transfer

Abstract

A core module of wireless sensing system is provided for receiving, processing and delivering environmental information, inclusive of a RF front-end circuit, a power control circuit, an analog front-end detection circuit and a baseband signal processor. A SOC (System on Chip) may be designed by including an electronic tag antenna, an impedance variation circuit and a sensor to form the wireless sensing system with the combination of a remote reader, such that the core module may be applied for wirelessly sensing the environmental information, such as physiological information of human heartbeat response, to achieve the effect of compactness, power saving and error detection.

Claims

1. A core module for wireless sensing system used to receive, process and output a sensed environmental information, wherein a sensor extracts environmental information and outputs a sensed environmental signal, including:

a RF front-end circuit, which is used to receive and process a RF input signal to generate a distance detection signal and a control instruction and power-on signal;

a power control circuit, which accepts the control of said control instruction and power-on signal to supply a DC regulation voltage;

an analog front-end detection circuit, which receives said DC regulation voltage and starts the function of receiving said sensed environmental signal that carries said sensed environmental information and output a digital environmental signal; and

a baseband signal processor, which receives said DC regulation voltage to receive said distance detection signal and said control instruction and power-on signal for outputting a demodulation control signal to said RF front-end circuit and outputting a power-off signal to the power control circuit, and receives and processes said digital environmental signal to output an impedance control signal that carries said sensed environmental information,

wherein said baseband signal processor includes;

a pulse generator, which generates a pulse signal;

a pulse interval encoding decoder, which inputs said control instruction and power-on signal and said pulse signal to generate a decoding signal;

an instruction decoder, which inputs said decoding signal to generate an instruction determination signal;

a five-bit cyclic redundancy check comparison circuit, which inputs and error detects said decoding signal to generate a check comparison signal;

a core finite state machine, which inputs said distance detection signal, said instruction determination signal and said check comparison signal to generate said demodulation control signal, said power-off signal, a divisor signal, a memory selection signal, a handshaking control signal and a memory access indication signal;

a returning frequency divider, which receives said divisor signal and said pulse signal to output a frequency divided pulse;

a pseudo random number generator, which receives said handshaking control signal to generate a handshaking signal;

a multiplexer, which receives said memory selection signal to transmit memory reading data and memory writing data;

a memory circuit, which is used to receive and store said memory writing data and to output said memory reading data;

a memory writing finite state machine, which receives said digital environmental signal and said memory access indication signal to output said memory writing data;

a memory reading finite state machine, which receives said frequency divided pulse, said handshaking signal, said memory access indication signal and said memory reading data and outputs a serial reading data; and

a FM0 encoder, which inputs and performs FM0 encoding for said serial reading data to output said impedance control signal on the basis of said frequency divided pulse.

2. The core module according to claim 1, wherein said RF front-end circuit includes:

a charge pump, which converts said RF input signal into a DC signal;

an amplitude shift keying demodulation circuit, which receives and processes said DC signal and said demodulation control signal to output said control instruction and power-on signal; and

a distance digital converter, which detects an internal voltage of said charge pump to generate said distance detection signal.

3. The core module according to claim 2, wherein methods that said amplitude shift keying demodulation circuit generates said control instruction and power-on signal include amplitude shift keying (ASK), phase shift keying (PSK), or frequency shift keying (FSK).

4. The core module according to claim 3, wherein said DC regulation voltage is divided into a digital DC regulation voltage for digital electronic elements and an analog DC regulation voltage for analog electronic components;

said power control circuit includes;

a start circuit, which receives said control instruction and power-on signal and said power-off signal to generate a power disable/enable signal;

a digital voltage regulation circuit, which receives said power disable/enable signal to generate or stop said digital DC regulation voltage; and

an analog voltage regulation circuit, which receives said power disable/enable signal to generate or stop said analog DC regulation voltage.

5. The core module according to claim 4, further including a cell or a digital reset circuit, wherein said cell is used to provide power for said digital voltage regulation circuit and said analog voltage regulation circuit to generate said DC regulation voltage;

said digital reset circuit is used to generate a reset signal for resetting digital memory elements in said baseband signal processor;

wherein said digital voltage regulation circuit or said analog voltage regulation circuit is low drop linear voltage regulation circuit or switching voltage regulation circuit.

6. The core module according to claim 1, wherein said analog front-end detection circuit includes:

a front-end amplifier, which receives and amplifies said sensed environmental signal and generate an amplified sensing signal;

an analog filter, which receives and filters said amplified sensing signal to generate a filtered signal;

a back-end amplifier, which receives and amplifies said filtered signal to generate an amplified filtered signal; and

an analog to digital converter, which converts said amplified filtered signal into said digital environmental signal.

7. The core module according to claim 6, wherein said analog filter is a low pass filter, a high pass filter, a band pass filter, a band rejection filter or the combination of above filters;

said front-end amplifier or said back-end amplifier is an open loop amplifier or a closed loop amplifier;

said analog filter is a continuous time process circuit or a discrete time process circuit;

said analog to digital converter is a single-slope converter, a dual-slope converter, a charge redistribution converter, a continuously successive approximation converter or a sigma delta data converter.

8. The core module according to claim 1, wherein said memory circuit includes a first memory and a second memory, which are used for writing said memory writing data and reading said memory reading data;

said memory circuit is composed of a static random access memory, a dynamic random access memory or an electrically programmable memory.

9. The core module according to claim 1, wherein said baseband signal processor has a structure of RFID communication protocol, Generation 2, Class 1.