Pulse synthesizing circuit

• US 9,287,867 B2
• Filed: 06/04/2014
• Issued: 03/15/2016
• Est. Priority Date: 06/11/2013
• Status: Active Grant

• Current Assignee: Onkyo Technology Kabushiki Kaisha
• Original Assignee: ONKYO Corporation (Onkyo Home Entertainment Corp.)
• Inventors: Nakanishi, Yoshinori, Kawaguchi, Tsuyoshi, Sekiya, Mamoru
• Primary Examiner(s): LE, DON P
• Application Number:
  US14/295,658
• Publication Number:
  US 20140361809A1
• Time in Patent Office: 650 Days
• Field of Search: 326/52, 326/59, 326/60
• US Class Current: 1/1
• CPC Class Codes: H03K 19/0002 Multistate logic H03K19/02 takes precedence
• CPC Class Codes: H03K 19/09443 using a combination of enhancement and depletion transistors
• CPC Class Codes: H03K 19/21 EXCLUSIVE-OR circuits, i.e. giving output if input signal exists at only one input; COINCIDENCE circuits, i.e. giving output only if all input signals are identical
• CPC Class Codes: H03M 3/30 Delta-sigma modulation
• CPC Class Codes: H04L 25/4923 using ternary codes H04L25/4927 takes precedence
• CPC Class Codes: H04L 25/4925 using balanced bipolar ternary codes

Abstract

A circuit having versatility synthesizes one-bit digital signals to generate a ternary signal. The pulse synthesizing circuit synthesizes one-bit digital signals from two DFFs to generate a ternary signal. The pulse synthesizing circuit has a first NOR gate, a second NOR gate, a third NOR gate, and three switches. The first switch is connected to a first electric potential, the second switch is connected to a second electric potential, and the third switch is connected to a third electric potential. The first to third switches are turned on/off according to logical values of the signals from the two DFFs, and any of the first electric potential, the second electric potential, and the third electric potential is set as an output potential so that a ternary signal is generated.

Claims

1. A pulse synthesizing circuit for synthesizing a first one-bit digital signal and a second one-bit digital signal to generate a ternary signal, the circuit comprising:

a logic circuit for outputting a first electric potential in a first case of a combination of a logical value of the first one-bit digital signal and a logical value of the second one-bit digital signal, outputting a second electric potential smaller than the first electric potential in a second case where a combination of a logical value of the first one-bit digital signal and a logical value of the second one-bit digital signal is different from the combination in the first case, and outputting a third electric potential between the first electric potential and the second electric potential in a third case where a combination of a logical value of the first one-bit digital signal and a logical value of the second one-bit digital signal is different from the combinations in the first case and the second case,

wherein

the logic circuit outputs the first electric potential when the logical value of the first one-bit digital signal is 1 and the logical value of the second one-bit digital signal is 0, outputs the second electric potential smaller than the first electric potential when the logical value of the first one-bit digital signal is 0 and the logical value of the second one-bit digital signal is 1, and outputs the third electric potential between the first electric potential and the second electric potential when the logical value of the first one-bit digital signal is 1 and the logical value of the second one-bit digital signal 1 or when the logical value of the first one-bit digital signal is 0 and the logical value of the second one-bit digital signal is 0.

2. The pulse synthesizing circuit according to claim 1, wherein the logic circuit includes a logical gate group and a switch group,

the switch group includes

a first switch connected to the first electric potential,

a second switch connected to the second electric potential, and

a third switch connected to the third electric potential, and

the logical gate group outputs a control signal for turning on the first switch when the logical value of the first one-bit digital signal is 1 and the logical value of the second one-bit digital signal is 0, outputs a control signal for turning on the second switch when the logical value of the first one-bit digital signal is 0 and the logical value of the second one-bit digital signal is 1, and outputs a control signal for turning on the third switch when the logical value of the first one-bit digital signal is 1 and the logical value of the second one-bit digital signal is 1 or when the logical value of the first one-bit digital signal is 0 and the logical value of the second one-bit digital signal is 0.

3. The pulse synthesizing circuit according to claim 2, wherein

the first switch is a first three-state buffer whose input terminal is connected to the first electric potential,

the second switch is a second three-state buffer whose input terminal is connected to the second electric potential,

the third switch is an analog switch whose input terminal is connected to the third electric potential,

output terminals of the first, second, and third switches are connected, and

the logical gate group includes

a first NOR gate for receiving an inverted signal of the first one-bit digital signal and the second one-bit digital signal, and performing a logical operation so as to output a signal to a control terminal of the first switch,

a second NOR gate for receiving the first one-bit digital signal and an inverted signal of the second one-bit digital signal, and performing a logical operation so as to output a signal to a control terminal of the second switch, and

a third NOR gate for receiving a control signal from the first NOR gate and a control signal from the second NOR gate, and performing a logical operation so as to output the control signals to the third switch.

4. A pulse synthesizing circuit for synthesizing a first one-bit digital signal and a second one-bit digital signal to generate a ternary signal, the circuit comprising:

a logic circuit for outputting a first electric potential in a first case of a combination of a logical value of the first one-bit digital signal and a logical value of the second one-bit digital signal, outputting a second electric potential smaller than the first electric potential in a second case where a combination of a logical value of the first one-bit digital signal and a logical value of the second one-bit digital signal is different from the combination in the first case, and outputting a third electric potential between the first electric potential and the second electric potential in a third case where a combination of a logical value of the first one-bit digital signal and a logical value of the second one-bit digital signal is different from the combinations in the first case and the second case,

wherein

the logic circuit outputs the first electric potential when the logical value of the first one-bit digital signal is 1 and the logical value of the second one-bit digital signal is 1, outputs the second electric potential smaller than the first electric potential when the logical value of the first one-bit digital signal is 0 and the logical value of the second one-bit digital signal is 0, and outputs the third electric potential between the first electric potential and the second electric potential when the logical value of the first one-bit digital signal is 1 and the logical value of the second one-bit digital signal is 0 or when the logical value of the first one-bit digital signal is 0 and the logical value of the second one-bit digital signal is 1,

the logic circuit includes a logical gate group and a switch group,

the switch group includes

a first switch connected to the first electric potential,

a second switch connected to the second electric potential, and

a third switch connected to the third electric potential, and

the logical gate group outputs a control signal for turning on the first switch when the logical value of the first one-bit digital signal is 1 and the logical value of the second one-bit digital signal is 1, outputs a control signal for turning on the second switch when the logical value of the first one-bit digital signal is 0 and the logical value of the second one-bit digital signal is 0, and outputs a control signal for turning on the third switch when the logical value of the first one-bit digital signal is 1 and the logical value of the second one-bit digital signal is 0 or when the logical value of the first one-bit digital signal is 0 and the logical value of the second one-bit digital signal is 1.

5. The pulse synthesizing circuit according to claim 4, wherein

the first switch is a P channel MOSFET,

the second switch is a N channel MOSFETs,

the third switch is an analog switch, and

the logical gate group includes

a NAND gate for receiving the first one-bit digital signal and the second one-bit digital signal, and performing a logical operation so as to output a control signal to a gate of the first switch,

a NOR gate for receiving the first one-bit digital signal and the second one-bit digital signal, and performing a logical operation so as to output a control signal to a gate of the second switch, and

an EXOR gate for receiving the control signal from the NAND gate and the control signal from the NOR gate, and performing a logical operation so as to output a control signal to the third switch.

6. A pulse synthesizing circuit for synthesizing a first one-bit digital signal and a second one-bit digital signal to generate a ternary signal, the circuit comprising:

a logic circuit for outputting a first electric potential in a first case of a combination of a logical value of the first one-bit digital signal and a logical value of the second one-bit digital signal, outputting a second electric potential smaller than the first electric potential in a second case where a combination of a logical value of the first one-bit digital signal and a logical value of the second one-bit digital signal is different from the combination in the first case, and outputting a third electric potential between the first electric potential and the second electric potential in a third case where a combination of a logical value of the first one-bit digital signal and a logical value of the second one-bit digital signal is different from the combinations in the first case and the second case,

wherein

the first one-bit digital signal and the second one-bit digital signal are signals subjected to delta sigma modulation.