Encryption device

• US 9,288,040 B2
• Filed: 08/14/2012
• Issued: 03/15/2016
• Est. Priority Date: 02/22/2010
• Status: Active Grant

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Endo, Tsukasa, Komano, Yuichi, Fujisaki, Koichi, Shimizu, Hideo, Ikeda, Hanae, Shimbo, Atsushi
• Primary Examiner(s): Holder, Bradley
• Application Number:
  US13/585,391
• Publication Number:
  US 20120307997A1
• Time in Patent Office: 1,309 Days
• Field of Search: 380/37, 380/28
• US Class Current: 1/1
• CPC Class Codes: H04L 9/003 for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA]
• CPC Class Codes: H04L 9/0631 Substitution permutation network [SPN], i.e. cipher composed of a number of stages or rounds each involving linear and nonlinear transformations, e.g. AES algorithms

Abstract

According to an embodiment, an encryption device performs encryption processing using an encryption key and calculates encrypted data from plain data. The encryption device includes: a register; an input unit configured to receive plain data; a first partial encryption unit configured to calculate first intermediate data from the plain data; a second partial encryption unit configured to calculate (i+1)-th intermediate data based on i-th intermediate data and the encryption key; a first transform unit configured to: transform j-th intermediate data into j-th transformed data; and store the j-th transformed data in the register; and a second transform unit configured to transform the j-th transformed data into the j-th intermediate data; a third partial encryption unit configured to calculate encrypted data from the N-th intermediate data. The second partial encryption unit is configured to repeat processing to calculate (j+1)-th intermediate data while j is equal to from 1 to N−1.

Claims

1. An encryption device comprising:

a register;

an input circuitry configured to receive plain data;

a first partial encryption circuitry configured to calculate first intermediate data from the plain data;

a second partial encryption circuitry configured to calculate (i+1)-th intermediate data based on i-th intermediate data and an encryption key, wherein i is an integer equal to or greater than one and smaller than N, and N is a predetermined integer equal to or greater than two;

a first transform circuitry configured to;

transform j-th intermediate data into j-th transformed data, wherein j is an integer equal to or greater than one and equal to or smaller than N; and

store the j-th transformed data in the register;

a second transform circuitry configured to transform the j-th transformed data stored in the register into the j-th intermediate data;

a third partial encryption circuitry configured to calculate encrypted data from the N-th intermediate data;

an output circuitry configured to output the encrypted data; and

a random number generation circuitry configured to;

generate a random number; and

store the random number in the register, wherein

the second partial encryption circuitry is further configured to repeat processing to calculate (j+1)-th intermediate data while j is equal to from 1 to N−

1, the processing being repeated based on the j-th intermediate data and the encryption key, the j-th intermediate data being transformed from the j-th transformed data by the second transform circuitry,

the first transform circuitry is further configured to;

transform the random number into a transformed random number using a predetermined first transform processing; and

transform the j-th intermediate data into the j-th transformed data,

the j-th transformed data being masked with the transformed random number, and

the second transform circuitry is further configured to;

transform the random number stored in the register into the transformed random number using the first transform processing; and

transform the j-th transformed data stored in the register into the j-th intermediate data,

the j-th intermediate data being released from the mask using the transformed random number, and

the transformed random number not being stored in the register.

2. An encryption device comprising:

a register;

an input circuitry configured to receive plain data;

a first partial encryption circuitry configured to calculate first intermediate data from the plain data;

a second partial encryption circuitry configured to calculate (i+1)-th intermediate data based on i-th intermediate data and an encryption key, wherein i is an integer equal to or greater than one and smaller than N, and N is a predetermined integer equal to or greater than two;

a first transform circuitry configured to;

transform j-th intermediate data into j-th transformed data, wherein j is an integer equal to or greater than one and equal to or smaller than N; and

store the j-th transformed data in the register;

a second transform circuitry configured to transform the j-th transformed data stored in the register into the j-th intermediate data;

a third partial encryption circuitry configured to calculate encrypted data from the N-th intermediate data;

an output circuitry configured to output the encrypted data; and

a random number generation circuitry configured to generate a random number, wherein

the second partial encryption circuitry is further configured to repeat processing to calculate (j+1)-th intermediate data while j is equal to from 1 to N−

1, the processing being repeated based on the j-th intermediate data and the encryption key, the j-th intermediate data being transformed from the j-th transformed data by the second transform engine,

the first transform circuitry is further configured to;

transform the random number into a transformed random number using a predetermined first transform processing;

store the transformed random number in the register; and

transform the j-th intermediate data into the j-th transformed data,

the j-th transformed data being masked with the random number, and

the second transform circuitry is further configured to;

transform the transformed random number stored in the register into the random number using a second transform processing,

the second transform processing transforming the transformed data after the transform by the first transform processing into the data before the transform by the first transform processing; and

transform the j-th transformed data stored in the register into the j-th intermediate data,

the j-th intermediate data being released from the mask using the random number, and

the random number not being stored in the register.

3. The encryption device according to claim 2, wherein the random number generation circuitry is further configured to:

generate a first random number and a second random number; and

store the generated second random number in the register,

the first transform circuitry is further configured to;

transform the first random number into the transformed random number, the transformed random number being masked using the second random number;

store the transformed random number in the register; and

transform the j-th intermediate data into the j-th transformed data, the j-th transformed data being masked using the first random number, and

the second transform circuitry is further configured to;

transform the transformed random number stored in the register into the first random number, the first random number being released from the mask using the second random number stored in the register; and

transform the j-th transformed data stored in the register into the j-th intermediate data, the j-th intermediate data being released from the mask using the first random number.