Circuits for efficient detection of vector signaling codes for chip-to-chip communication using sums of differences

• US 9,288,082 B1
• Filed: 05/15/2013
• Issued: 03/15/2016
• Est. Priority Date: 05/20/2010
• Status: Active Grant

• Current Assignee: Kandou Labs, SA
• Original Assignee: Kandou Labs, SA
• Inventors: Ulrich, Roger, Hunt, Peter
• Primary Examiner(s): Wong, Linda
• Application Number:
  US13/895,206
• Time in Patent Office: 1,035 Days
• Field of Search: 375/219, 375/220, 375/222, 375229-236, 37524026-24029, 375/259, 375/285, 375/284, 375/295, 375/297, 375/316, 375/317, 375/318, 375/319, 375/324, 375/326, 375/338, 375/339, 375/340, 375/341, 375/346, 375/347, 375/350, 375/354, 375/19, 375/240.23, 375/240.24, 375/240.1, 375/240.11, 375/278, 375/260, 375/296, 375/299, 330/252, 330/255, 330/278, 330/288, 330/307, 330/51, 330/54, 330/69, 330/72, 330/98, 330/85, 330/108
• US Class Current: 1/1
• CPC Class Codes: H04L 2025/03363 Multilevel H04L2025/03369 takes precedence
• CPC Class Codes: H04L 2025/03426 transmission using multiple-input and multiple-output channels
• CPC Class Codes: H04L 2025/03789 Codes therefore
• CPC Class Codes: H04L 25/02 Details ; arrangements for supplying electrical power along data transmission lines systems for transmitting signals via power distribution lines H04B3/54
• CPC Class Codes: H04L 25/0274 Arrangements for ensuring balanced coupling
• CPC Class Codes: H04L 25/0294 Provision for current-mode coupling
• CPC Class Codes: H04L 25/03006 Arrangements for removing intersymbol interference
• CPC Class Codes: H04L 25/03878 Line equalisers; line build-out devices
• CPC Class Codes: H04L 25/08 Modifications for reducing interference; Modifications for reducing effects due to line faults ; Receiver end arrangements for detecting or overcoming line faults
• CPC Class Codes: H04L 25/14 Channel dividing arrangements , i.e. in which a single bit stream is divided between several baseband channels and reassembled at the receiver
• CPC Class Codes: H04L 25/4917 using multilevel codes

Abstract

In a detection circuit, inputs correspond to received indications of vector signaling code words received by a first integrated circuit from a second integrated circuit. With four inputs, the circuit compares a first pair to obtain a first difference result and compares a second pair, disjoint from the first pair, to obtain a second difference result. The first and second difference results are then summed to form an output function. A system might use a plurality of such detection circuits to arrive at an input word. The circuit can include amplification, equalization, and input selection with efficient code word detection. The vector signaling code can be a Hadamard matrix code encoding for three input bits. The circuit might also have frequency-dependent gain, a selection function that directs one of the summation function result or the first difference result to the output function, variable gain, and/or a slicer.

Claims

1. A circuit comprising:

a first differential amplifier configured to generate a first difference signal between signals received on a first pair of selected inputs representing symbols of a vector signaling code word of an orthogonal vector signaling code received via a multi-wire communications bus, and a second differential amplifier configured to generate a second difference signal between signals received on a second pair of selected inputs representing symbols of the vector signaling code word of the orthogonal vector signaling code received via the multi-wire communications bus, the first pair of selected inputs and the second pair of selected inputs being disjoint;

a summation circuit comprising load impedance elements connected to the first differential amplifier and the second differential amplifier, the summation circuit configured to generate a sum-of-differences output signal by combining the first difference signal and the second difference signal; and

an output circuit for generating, based on the sum-of-differences output signal, a portion of a respective code identification result signal that fully identifies the received code word of the orthogonal vector signaling code.

2. The circuit of claim 1, wherein the output circuit is implemented by distinct circuit elements.

3. The circuit of claim 1, wherein the output circuit is implemented by interconnections of circuit elements.

4. The circuit of claim 1, wherein the orthogonal vector signaling code is a Hadamard matrix code.

5. The circuit of claim 1, wherein each input of the first pair of selected inputs and the second pair of selected inputs carry signals selected from a set of a high positive value, a low positive value, a low negative value, and a high negative value, representable, respectively as {−

1, −

1/3, 1/3, 1}, wherein each code word of the orthogonal vector signaling code is a permutation of the symbol set {1, −

1/3, −

1/3, −

1/3} or a permutation of the symbol set {−

1, 1/3, 1/3, 1/3}.

6. The circuit of claim 1, wherein the first pair of inputs and the second pair of inputs collectively encode for a set of three input bits.

7. The circuit of claim 1, further comprising a first frequency-dependent gain circuit connected to the first differential amplifier and a second frequency-dependent gain circuit connected to the second differential amplifier, the first and second frequency-dependent gain circuits configured to provide providing an signal equalization or signal peaking.

8. The circuit of claim 1, further comprising a selection function circuit that directs one of the sum-of-differences output signal or the first difference signal to the output circuit.

9. The circuit of claim 8, further comprising a negative feedback loop including the output circuit, the selection circuit function, or both.

10. The circuit of claim 8, wherein the selection circuit is a multiplexor.

11. The circuit of claim 1, wherein the output circuit incorporates variable gain.

12. The circuit of claim 1, wherein the output circuit incorporates a digital threshold or slicer.

13. The circuit of claim 1, wherein the output circuit incorporates a time sampling function.

14. The circuit of claim 1, further comprising a sampling circuit configured to sample the portion of the respective code identification result signal.

15. The circuit of claim 14, further comprising a slicer configured to generate a binary output based on the sampled portion of the respective code identification result signal.

16. The circuit of claim 1, further comprising a threshold gate configured to generate a binary output based on the portion of the respective code identification result signal.

17. The circuit of claim 16, wherein the threshold gate is a Schmidt trigger.

18. The circuit of claim 1, wherein the received signals correspond to analog voltages.

20. The circuit of claim 1, wherein the load impedance elements are selected from the group consisting of:

at least two inductors;

at least two resistors; and

at least two current sources.

19. A system comprising:

a plurality of pairs of differential amplifiers connected to a multi-wire communication bus, each pair of the plurality of pairs of differential amplifiers receiving inputs corresponding to symbols of a received code word of a vector code, and each differential amplifier of the pair of differential amplifiers configured to generate difference signals;

a plurality of load impedance element pairs, each load impedance element pair of the plurality of load impedance element pairs is connected to a respective pair of differential amplifiers, each load impedance pair configured to generate a sum-of-difference signal based on the generated difference signals; and

a plurality of output circuits, each output circuit of the plurality of output circuits configured to generate a respective code identification result signal responsive to the sum-of-difference signal, wherein the respective code identification result signals from the plurality of output circuits fully identifies the received code word.