Continuous-time linear equalizer for high-speed receiving unit

• US 9,288,085 B2
• Filed: 03/26/2015
• Issued: 03/15/2016
• Est. Priority Date: 04/11/2014
• Status: Active Grant

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Bulzacchelli, John F., Francese, Pier Andrea, Liu, Yong, Toifl, Thomas H.
• Primary Examiner(s): Guarino, Rahel
• Application Number:
  US14/669,225
• Publication Number:
  US 20150295736A1
• Time in Patent Office: 355 Days
• Field of Search: 375/233, 375/232, 375/229, 375/257, 333/28.R, 370/419, 370/463
• US Class Current: 1/1
• CPC Class Codes: H04B 1/123 using adaptive balancing or compensation means adaptive filter circuits and algorithms H03H
• CPC Class Codes: H04L 25/03057 with a recursive structure H04L25/03031 takes precedence
• CPC Class Codes: H04L 25/03063 using fractionally spaced delay lines or combinations of fractionally and integrally spaced taps
• CPC Class Codes: H04L 25/03885 adaptive

Abstract

A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal includes a signal line configured to provide an equalized output voltage, and an active peaking control unit, including a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail; a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of transistors according to first setting signals.

Claims

1. A continuous-time linear equalizer for use in a receiving unit of a high-speed data transmission system for receiving an input signal, comprising:

a signal line configured to provide an equalized output voltage; and

an active peaking control unit, comprising;

a predetermined first number of active peaking transistors each coupled between the signal line and a power supply rail;

a peaking resistor that couples gate terminals of each of the active peaking transistors to the signal line; and

a first number of first setting switches each associated with each of the first number of active peaking transistors to activate a predetermined number of the first number of active peaking transistors according to first setting signals.

2. The continuous-time linear equalizer of claim 1, further comprising a gain stage configured to couple the input signal to the signal line to provide one of a predetermined or a variable transconductance.

3. The continuous-time linear equalizer of claim 2, further comprising a number of serially coupled stages each at least comprising a gain stage and an active peaking control unit, wherein particularly the active peaking control unit is coupled to a different potential of the power supply rail.

4. The continuous-time linear equalizer of claim 1, further comprising a further peaking control unit having a first number of diode-connected transistors each coupled between the signal line and the power supply rail, and a first number of complementary first setting switches each associated with each of the first number of diode-connected transistors to activate a predetermined number of the first number of transistors according to inverted first setting signals, so that a total number of activated active peaking transistors and a total number of the diode-connected transistors are the same.

5. The continuous-time linear equalizer of claim 1, further comprising a peaking capacitor unit having a predetermined second number of peaking capacitors each coupled between the gate-connected terminal of the peaking resistor and the power supply rail, and a second number of second setting switches each associated with each of the second number of peaking capacitors to activate a predetermined number of the second number of peaking capacitors according to second setting signals.

6. The continuous-time linear equalizer of claim 1, further comprising a bandwidth control unit having a predetermined third number of load capacitors each coupled between the signal line and the power supply rail, and a third number of third setting switches each associated with each of the third number of load capacitors to activate a predetermined number of the third number of load capacitors according to third setting signals.

7. The continuous-time linear equalizer of claim 4, further comprising a current source unit which is configured as a predetermined fourth number of current source transistors each connected in series with a respective fourth setting switch, wherein a number of the fourth setting switches are configured to be activated in accordance with fourth setting signals to set a gain of the continuous-time linear equalizer.

8. The continuous-time linear equalizer of claim 7, wherein the active peaking control unit, the further peaking control unit and the current source unit are configured to reduce a number of activated diode-connected transistors of the further peaking control unit in accordance with the number of activated current source transistors.

9. The continuous-time linear equalizer of claim 1, further comprising a conversion unit configured to convert a voltage of the signal line to a current supplied to a summing node, so as to allow a summing up of currents provided by a decision feedback equalizer.

10. The continuous-time linear equalizer of claim 9, further comprising a track-and-hold switch to couple the signal line to the conversion unit.

11. The continuous-time linear equalizer of claim 9, further comprising an even and odd track-and-hold switch to couple the signal line to two separated conversion units.

12. The continuous-time linear equalizer of claim 9, further comprising an even and odd track-and-hold switch to couple the output of the conversion unit to an even and an odd summing node, respectively.

13. The continuous-time linear equalizer of claim 1, further comprising:

a common gate stage transistor which is coupled to one terminal with an input of the continuous-time linear equalizer and to a further terminal with the signal line, wherein a gate terminal of the common gate stage transistor is coupled to one of a predetermined control voltage or an output of a regulation amplifier providing a comparison result between a control voltage and the input signal; and

a current source configured to supply a predetermined current to the signal line.

14. The continuous-time linear equalizer of claim 1, wherein the continuous-time linear equalizer is implemented in a differential configuration and has differential signal lines, wherein the active peaking transistors in the one or more units are mirrored.

15. The continuous-time linear equalizer of claim 14, further comprising a differential negative impedance unit comprising a fifth number of cross-coupled transistor pairs each comprising two cross-coupled transistors, wherein gate terminals of the cross-coupled transistors are coupled to the respective other differential signal line and wherein the one terminal of each of the cross-coupled transistors is coupled to a respective one of the signal lines and another terminal of each of the cross-coupled transistors is coupled to a respective one of fifth setting switches to activate the respective cross-coupled transistor pair according to fifth setting signals, wherein the gate terminals of each pair of the cross-coupled transistors are interconnected with a cross capacity.

16. The continuous-time linear equalizer of claim 14, wherein the active peaking control unit further comprises a first number of cross-coupling capacitor pairs each including two capacitors each coupling a gate terminal of a respective one of the active peaking transistors of the cross-coupled transistor pair to a terminal of a respective other of the active peaking transistors of the respective active peaking transistor pair.

17. The continuous-time linear equalizer of claim 14, wherein a differential gain stage is formed for coupling a second input signal to a respective signal line of the differential signal lines for providing one of a predetermined or variable transconductance.

18. The continuous-time linear equalizer of claim 17, wherein the differential gain stage is formed as a telescopic stage.

19. The continuous-time linear equalizer of claim 14, wherein a differential conversion unit comprises regenerative cascaded transistor pairs which are coupled serially to respective conversion transistors and are configured with transistors being cross-coupled with respect to the differential signal lines.

20. The continuous-time linear equalizer of claim 1, further comprising a setting unit configured to provide respective setting signals according to one of a predetermined setting or minimizing a bit error rate.

21. The continuous-time linear equalizer of claim 1, wherein a resistance of the active peaking resistor is chosen so that a frequency where a numerator of a transfer function of the continuous-time linear equalizer is zero is smaller than a frequency of the poles of a denominator of the transfer function.