Controlling a turbo mode frequency of a processor

• US 9,292,068 B2
• Filed: 03/01/2013
• Issued: 03/22/2016
• Est. Priority Date: 10/31/2011
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Ananthakrishnan, Avinash N., Rotem, Efraim, Rajwan, Doron, Weissmann, Eliezer, Wells, Ryan, Shulman, Nadav
• Primary Examiner(s): Vo, Tim T
• Assistant Examiner(s): Huynh, Kim T.
• Application Number:
  US13/782,539
• Publication Number:
  US 20130179705A1
• Time in Patent Office: 1,117 Days
• Field of Search: 713300-344
• US Class Current: 1/1
• CPC Class Codes: G06F 1/26 Power supply means, e.g. regulation thereof for memories G11C
• CPC Class Codes: G06F 1/3206 Monitoring of events, devices or parameters that trigger a change in power modality
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3243 Power saving in microcontroller unit
• CPC Class Codes: G06F 1/3287 by switching off individual functional units in the computer system
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

In one embodiment, the present invention includes a multicore processor with a power controller to control a frequency at which the processor operates. More specifically, the power controller can limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions occurring responsive to power state events, thus avoiding the overhead of operations performed in handling such transitions. Other embodiments are described and claimed.

Claims

1. An article comprising a non-transitory machine-accessible storage medium including instructions that when executed cause a system to:

analyze a plurality of power state change events of a multicore processor including a plurality of cores during an evaluation interval to determine a number of frequency transitions responsive to the plurality of power state change events for each of N-core turbo frequencies;

select one of the N-core turbo frequencies to be a maximum operating frequency of the multicore processor for a next operating interval based at least in part on the number of frequency transitions, the selected N-core turbo frequency less than a configured maximum operating frequency of the multicore processor; and

control the plurality of cores to operate at no higher than the selected N-core turbo frequency for the next operating interval.

2. The article of claim 1, further comprising instructions that when executed enable the system to receive a turbo mode request for a first core of the multicore processor from a scheduler during the next operating interval, and control the first core to operate at the selected N-core turbo frequency.

3. The article of claim 1, further comprising instructions that when executed enable the system to update a first entry of a table on a power state change event, if a frequency transition would be performed responsive to the power state change event if the multicore processor were operating at an N-core turbo frequency associated with the first entry.

4. The article of claim 3, further comprising instructions that when executed enable the system to select the maximum operating frequency based on the table and store the maximum operating frequency in a configuration register of the multicore processor.

5. The article of claim 4, wherein the selection of the maximum operating frequency comprises selection of the maximum operating frequency to be the N-core turbo frequency associated with an entry of the table having a counter value less than a threshold.

6. The article of claim 3, further comprising instructions that when executed enable the system to update the first entry of the table associated with the N-core turbo frequency when a number of the plurality of cores in an active state after the power state transition event is greater than N.

7. The article of claim 6, wherein update of the first entry includes incrementation of the first entry.

8. The article of claim 3, further comprising instructions that when executed enable the system to not update a second entry of the table associated with an N+1-core turbo frequency when a number of the plurality of cores in an active state after the power state change event is less than or equal to N+1.

9. The article of claim 3, further comprising instructions that when executed enable the system to update a plurality of entries of the table responsive to the power state change event when a frequency transition would be performed responsive to the power state change event if the multicore processor were operating at the N -core turbo frequency associated with each of the plurality of entries prior to the power state change event.

10. A processor comprising:

a plurality of cores to independently execute instructions; and

a power controller to control a frequency at which the processor is to operate, the power controller to limit a maximum operating frequency of the processor to less than a configured maximum operating frequency to enable a reduction in a number of frequency transitions that occur responsive to power state events, wherein the power controller is coupled to a table including a plurality of entries each associated with an N-core turbo frequency and to store a counter value corresponding to a first number of frequency transitions during an evaluation interval if the processor were to operate at the N-core turbo frequency, and analyze a plurality of power state change events during the evaluation interval to determine the first number of frequency transitions.

11. The processor of claim 10, wherein the power controller is to limit the maximum operating frequency to be an N-core turbo frequency associated with an entry of the table having a counter value less than a threshold.

12. The processor of claim 11, wherein when a plurality of entries have a counter value less than the threshold, the power controller is to select the highest N-core turbo frequency associated with the plurality of entries.

13. The processor of claim 11, wherein the power controller is to receive a turbo mode request from a scheduler and to cause the processor to operate at the N-core turbo frequency.

14. The processor of claim 10, wherein responsive to the maximum operating frequency limit, when N cores of the processor are in an active state, the processor is to operate at no higher than an N+1-core turbo frequency during a turbo mode.

15. A system comprising:

a multicore processor including a plurality of cores and a controller to, responsive to a power state change event of at least one core of the plurality of cores, determine a number of cores of the multicore processor to be in an active state after the power state change event, and determine whether to update a first entry of a turbo demotion table associated with a N-core turbo frequency based at least in part on whether a frequency transition would be performed if the multicore processor were in operation at the N-core turbo frequency, the turbo demotion table including a plurality of entries each associated with an N-core turbo frequency and to store a counter value corresponding to a potential number of frequency transitions during an evaluation interval; and

a dynamic random access memory (DRAM) coupled to the multicore processor.

16. The system of claim 15, wherein the controller is to update the first entry if the frequency transition would be performed.

17. The system of claim 15, wherein the controller is to maintain and update the turbo demotion table for an evaluation interval having a plurality of power state change events.

18. The system of claim 17, wherein the controller is to access the turbo demotion table after the evaluation interval to identify the entry of the turbo demotion table having a counter field value less than a frequency transition threshold and associated with a highest N-core turbo frequency, and to limit a maximum operating frequency of the multicore processor to the highest N-core turbo frequency.