Micro-threaded memory

• US 9,292,223 B2
• Filed: 05/23/2013
• Issued: 03/22/2016
• Est. Priority Date: 11/29/2004
• Status: Active Grant

• Current Assignee: K.Mizra LLC
• Original Assignee: Rambus Inc.
• Inventors: Ware, Frederick A., Hampel, Craig E., Richardson, Wayne S., Bellows, Chad A., Lai, Lawrence
• Primary Examiner(s): Cygiel, Gary W
• Application Number:
  US13/901,014
• Publication Number:
  US 20130265842A1
• Time in Patent Office: 1,034 Days
• Field of Search: 711/157, 711/167, 711/168
• US Class Current: 1/1
• CPC Class Codes: G06F 3/0613 in relation to throughput
• CPC Class Codes: G06F 3/0659 Command handling arrangements, e.g. command buffers, queues, command scheduling
• CPC Class Codes: G06F 3/0673 Single storage device
• CPC Class Codes: G11C 11/4076 Timing circuits for regeneration management G11C11/406
• CPC Class Codes: G11C 11/4097 Bit-line organisation, e.g. bit-line layout, folded bit lines
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1042 using interleaving techniques, i.e. read-write of one part of the memory while preparing another part
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: G11C 8/06 Address interface arrangements, e.g. address buffers

Abstract

A micro-threaded memory device. A plurality of storage banks are provided, each including a plurality of rows of storage cells and having an access restriction in that at least a minimum access time interval must transpire between successive accesses to a given row of the storage cells. Transfer control circuitry is provided to transfer a first amount of data between the plurality of storage banks and an external signal path in response to a first memory access request, the first amount of data being less than a product of the external signal path bandwidth and the minimum access time interval.

Claims

1. A synchronous memory device to sequentially receive commands over an external request link from a memory controller, the sequential-received commands including respective row activate commands and column access commands, the synchronous memory device comprising:

first and second bank groups, each comprising at least two storage arrays; and

a request interface to sequentially-receive the commands from the external request link,

the request interface having row control circuitry to service two row activate commands sequentially-received from the external request link and addressed to respective storage arrays in different ones of the bank groups with a shorter intervening interval than the row control circuitry can service two row activate commands sequentially-received from the external request link and addressed to respective storage arrays in a same one of the bank groups, wherein as a result of the two row activate commands, respective rows in each of the addressed storage arrays are concurrently active,

the request interface having column control circuitry to service two column access commands sequentially-received from the request link and directed to respective, active rows in respective storage arrays in different ones of the bank groups with a shorter intervening interval than the column control circuitry can service two column access commands directed to one or more active rows in a same one of the bank groups.

2. The synchronous memory device of claim 1, further comprising a first data serialization register to receive read data responsive to sequentially-received column access commands addressed to the first bank group, and a second data serialization register to receive read data responsive to sequentially-received column access commands addressed to the second bank group.

3. The synchronous memory device of claim 2, wherein the first and second data serialization registers are coupled to a common set of external data connections.

4. The synchronous memory device of claim 2, wherein the first and second bank groups are organized into different quadrants of the device, and wherein the external data connections are located between the quadrants.

5. The synchronous memory device of claim 1, wherein the first and second bank groups are organized into different quadrants of the device.

6. The synchronous memory device of claim 1, wherein the request interface comprises a request decoder embodied as a portion of the row control circuitry and column control circuitry, the request decoder to determine for each sequentially-received row activate command and each sequentially-received column access command an addressed one of the bank groups.

7. The synchronous memory device of claim 6, wherein the request decoder generates separately-timed row control signals dedicated to each of the bank groups, and wherein the request decoder is to generate, responsive to each sequentially-received row activate command, a row control signal for the bank group addressed by the respective, sequentially-received row activate command.

8. The synchronous memory device of claim 7, wherein the storage arrays of each bank group are organized as plural banks, and wherein the request interface further comprises, for each bank group, a register to store a row address and a bank address indicating which of the banks in the group is addressed by a row activate command.

9. The synchronous memory device of claim 8, wherein the request decoder is to generate separately-timed column control signals dedicated to each of the bank groups, and wherein the request decoder is to generate, responsive to each sequentially-received column access command, column control signals for the bank group addressed by the respective, sequentially-received column access command.

10. The synchronous memory device of claim 9, the request interface further comprising, for each bank group, a register to store a column address and a bank address indicating which of the banks in the group is addressed by a column access command.

11. The synchronous memory device of claim 1, further comprising at least one data serialization register to receive read data responsive to sequentially-received column access commands addressed to the first and second bank groups, and to serialize the received read data for transmission over at least one external serial link, wherein the degree of serialization and a number of the at least one external serial links over which the read data is transmitted are configurable.

12. The synchronous memory device of claim 1, further comprising a data interface to exchange read data obtained pursuant to memory read transactions with an external data path, the data interface operable to exchange first read data obtained from the first bank group over a first link subset of the external data path, the data interface to exchange second read data obtained from the second bank group over a second link subset of the external data path.

13. The synchronous memory device of claim 1, further comprising a data interface to exchange read data obtained pursuant to memory read transactions with an external data path, the data interface operable to transmit the read data synchronously with at least one strobe signal.

14. The synchronous memory device of claim 1, wherein each of the first and second bank groups is associated with at least four banks.

15. The synchronous memory device of claim 1, further comprising at least one data serialization register to receive read data responsive to column access commands addressed to the first and second bank groups, and a data interface to transmit the read data as at least one differential, serial signal having a minimum transition density for clock decoding.

16. A synchronous memory device to sequentially-receive memory read commands over an external request link from a memory controller, the sequentially-received memory read commands including respective, row activate commands and column access commands, the synchronous memory device comprising:

first and second bank groups, each comprising at least two storage arrays;

a request interface to sequentially-receive the commands from the external request link;

circuitry coupled to the request interface and responsive to the commands to cause the retrieval of read data associated with each memory read transaction from memory cells of at least one of the storage arrays; and

a data interface to externally exchange the read data;

wherein the memory device is characterized by a first timing requirement for concurrently active rows, from a first row activate command sequentially-received from the external link and directed to a storage array in the first bank group to another row activate command sequentially-received from the external link and directed to another storage array in the first bank group, and a second timing requirement for concurrently active rows from the first row activate command to another row activate command sequentially-received from the external link and directed to a storage array in the second bank group, the second timing requirement being shorter than the first timing requirement; and

wherein the memory device is further characterized by a third timing requirement from a first column access command sequentially-received from the external link and directed to a first open row in a storage array in the first bank group to another column access command sequentially-received from the external link and directed to an open row associated with the first bank group, and a fourth timing requirement from the first column access command to another column access command sequentially-received from the external link directed to an open row associated with the second bank group, the fourth timing requirement being shorter than the third timing requirement.

17. The synchronous memory device of claim 16, wherein the circuitry comprises a request decoder to generate separately-timed row control signals dedicated to each of the bank groups, the request decoder generating, responsive to each respective row activate command, a row control signal for a bank group addressed by a respective row activate command, the request decoder operable to generate the separately-timed row control signals within a period shorter than the first timing requirement when successive row activate commands are directed to different bank groups.

18. The synchronous memory device of claim 17, wherein the storage arrays of each bank group are organized as plural banks, the circuitry further comprising, for each bank group, a register to store a row address and a bank address indicating which of the banks in the group is addressed by a row activate command.

19. The synchronous memory device of claim 16, wherein the circuitry comprises a request decoder operable to generate separately-timed column control signals dedicated to each of the bank groups, the request decoder operable to generate column control signals within a period shorter than the third timing requirement when successive column access commands are directed to different bank groups.

20. The synchronous memory device of claim 16, further comprising a first data serialization register to receive read data responsive to sequentially-received column access commands addressed to the first bank group, and a second data serialization register to receive read data responsive to sequentially-received column access commands addressed to the second bank group, wherein the first and second data serialization registers are coupled to a common set of external data connections.

21. The synchronous memory device of claim 16, the request interface further comprising, for each bank group, a register to store a column address and a bank address indicating which of the banks in the group is addressed by a column access command.

22. A synchronous memory device to sequentially-receive commands over an external request link from a memory controller, the sequential-received commands including respective row activate commands and column access commands, the synchronous memory device comprising:

first and second bank groups, each comprising at least two storage arrays;

a request interface to sequentially-receive the commands from the external request link;

row control circuitry coupled to the request interface to open a row in at least one addressed storage array responsive to each row activate command;

column control circuitry coupled to the request interface to cause retrieval of column-specified read data from an open row in at least one addressed storage array responsive to each column access command;

a data interface to externally exchange the column-specified read data;

wherein the row control circuitry is characterized by a first timing requirement for concurrently open rows, from a first row activate command sequentially-received from the external request link to open a first row in a storage array in the first bank group to another row activate command sequentially-received from the external request link to open another row in another storage array in the first bank group, and a second timing requirement for concurrently open rows, from the first row activate command to another row activate command sequentially-received from the external request link to open another row associated with the second bank group, the second timing requirement being shorter than the first timing requirement; and

wherein the column control circuitry is characterized by a third timing requirement from a first column access command sequentially-received from the external request link directed to the first open row to another column access command sequentially-received from the external request link directed to an open row in the first bank group, and a fourth timing requirement from the first column access command sequentially-received from the external request link to another column access command sequentially-received from the external request link directed to an open row in the second bank group, the fourth timing requirement being shorter than the third timing requirement.

23. The synchronous memory device of claim 22, wherein each of the external commands comprises an address field having portions dedicated respectively to each of bank group, bank within a bank group, and address within a bank.