Detection and decoding in flash memories using correlation of neighboring bits and probability based reliability values

• US 9,292,377 B2
• Filed: 12/31/2012
• Issued: 03/22/2016
• Est. Priority Date: 01/04/2011
• Status: Active Grant

• Current Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Original Assignee: Seagate Technology LLC (Seagate Technology Holdings Plc)
• Inventors: Alhussien, Abdel Hakim S., Haratsch, Erich F.
• Primary Examiner(s): Shah, Sanjiv
• Assistant Examiner(s): Gossage, Glenn
• Application Number:
  US13/731,766
• Publication Number:
  US 20130185599A1
• Time in Patent Office: 1,177 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/1048 using arrangements adapted for a specific error detection or correction feature
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 2212/1032 Reliability improvement, data loss prevention, degraded operation etc
• CPC Class Codes: G11C 11/56 using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
• CPC Class Codes: G11C 16/34 Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention

Abstract

Methods and apparatus are provided for detection and decoding in flash memories using a correlation of neighboring bits or errors in neighboring bits. Data from a flash memory device is processed by obtaining one or more read values for a plurality of bits in one or more pages of the flash memory device; converting the one or more read values for the plurality of bits to a reliability value, such as a log likelihood ratio (LLR), for a given bit among said plurality of bits based on a probability that a data pattern was written to the plurality of bits given that a particular pattern was read from the plurality of bits; and decoding the given bit in a given page of the one or more pages using the reliability value. The probability may be obtained from one or more transition probability tables, or may be based on one or more reference cells, prior decoded decisions or performance factors.

Claims

1. A method for processing data from a flash memory device, comprising:

obtaining one or more read values for a plurality of bits in one or more pages of said flash memory device;

converting said one or more read values for said plurality of bits to a reliability value for a given bit among said plurality of bits based on a probability that a data pattern was written to said plurality of bits given that a particular pattern was read from said plurality of bits; and

decoding said given bit in a given page of said one or more pages using said reliability value.

2. The method of claim 1, wherein said one or more read values comprise one or more of a hard value and a soft value.

3. The method of claim 1, wherein said flash memory device comprises a plurality of cells each capable of storing at least two data levels per cell.

4. The method of claim 1, wherein said decoding comprises a Low Density Parity Check (LDPC) Message Passing decoding.

5. The method of claim 1, wherein said decoding is performed in real-time.

6. The method of claim 1, wherein said reliability value comprises one or more of a log-likelihood ratio and an approximation of a log-likelihood ratio.

7. The method of claim 1, further comprising the step of generating said reliability value for said given bit in said given page using one or more of (i) read values for additional bits of said one or more pages, and (ii) read values for one or more additional bits of at least one additional page in a same wordline as said given page.

8. The method of claim 1, wherein said probability that said data pattern was written to said plurality of bits given that said particular pattern was read from said plurality of bits is obtained from one or more tables.

9. The method of claim 8, wherein one or more of (i) said data pattern and (ii) said particular pattern comprises said given bit and at least one additional bit in said given page.

10. The method of claim 8, wherein one or more of (i) said data pattern and (ii) said particular pattern comprises said given bit and at least one additional bit in a same cell as said given bit.

11. The method of claim 8, wherein one or more of (i) said data pattern and (ii) said particular pattern comprises said given bit and at least one additional bit in a different cell as said given bit.

12. The method of claim 1, wherein said probability that said data pattern was written to said plurality of bits given that said particular pattern was read from said plurality of bits is based on one or more reference cells.

13. The method of claim 1, wherein said probability that said data pattern was written to said plurality of bits given that said particular pattern was read from said plurality of bits is based on one or more prior decoded decisions.

14. The method of claim 1, wherein said probability that said data pattern was written to said plurality of bits given that said particular pattern was read from said plurality of bits is based on one or more performance factors of said flash memory device.

15. The method of claim 14, wherein said performance factors of said flash memory device comprise one or more of endurance, number of program/erase cycles, number of read cycles, retention time, temperature, temperature changes, process corner, inter-cell interference (ICI) impact, location of one or more memory cells within a memory array of said flash memory device, location of a wordline from which said one or more read values is obtained, location of said given page from which said one or more read values is obtained, location of said given page within a wordline from which said one or more read values is read, and a pattern of aggressor cells.

16. The method of claim 14, wherein one or more of said performance factors of said flash memory device can be varied for one or more of different bits within a memory cell, different pages within a wordline, different bit lines, and different hard read data values.

17. The method of claim 1, wherein said converting of said one or more read values for said plurality of bits to the reliability value employs a distribution marginalization.

18. The method of claim 17, wherein said distribution marginalization computes the reliability value for said given bit given that a first pattern was read, wherein said reliability value for said given bit is based on multiple probabilities for different patterns that were written given that said first pattern was read.

19. A tangible machine-readable recordable storage medium for processing data from a flash memory device, wherein one or more software programs stored on said storage medium when executed by one or more processing devices implement the steps of the method of claim 1.

20. A flash memory system, comprising:

a reliability unit for converting one or more read values for a plurality of bits in one or more pages to a reliability value for a given bit among said plurality of bits based on a probability that a data pattern was written to said plurality of bits given that a particular pattern was read from said plurality of bits; and

a decoder for decoding said given bit in a given page of said one or more pages using said reliability value.

21. The flash memory system of claim 20, wherein said decoding is performed in real-time.

22. The flash memory system of claim 20, wherein said reliability value comprises one or more of a log-likelihood ratio and an approximation of a log-likelihood ratio.

23. The flash memory system of claim 20, wherein said reliability unit is configured to generate said reliability value for said given bit in said given page using one or more of (i) read values for additional bits of said given page, and (ii) read values for one or more additional bits of at least one additional page in a same wordline as said given page.

24. The flash memory system of claim 20, wherein said probability that said data pattern was written to said plurality of bits given that said particular pattern was read from said plurality of bits is obtained from one or more tables.

25. The flash memory system of claim 24, wherein one or more of (i) said data pattern and (ii) said particular pattern comprises one or more of (i) said given bit and at least one additional bit in said given page;

(ii) said given bit and at least one additional bit in a same cell as said given bit; and

(iii) said given bit and at least one additional bit in a different cell as said given bit.

26. The flash memory system of claim 20, wherein said probability that said data pattern was written to said plurality of bits given that said particular pattern was read from said plurality of bits is based on one or more of one or more reference cells, one or more prior decoded decisions and one or more performance factors of a flash memory device accessed by said flash memory system.

27. The flash memory system of claim 26, wherein said performance factors of said flash memory device comprise one or more of endurance, number of program/erase cycles, number of read cycles, retention time, temperature, temperature changes, process corner, inter-cell interference (ICI) impact, location of one or more memory cells within a memory array of said flash memory system, location of a wordline from which said one or more read values is obtained, location of said given page from which said one or more read values is obtained, location of said given page within a wordline from which said one or more read values is read, and a pattern of aggressor cells.

28. The flash memory system of claim 26, wherein one or more of said performance factors of said flash memory device can be varied for one or more of different bits within a memory cell, different pages within a wordline, different bit lines, and different hard read data values.

29. The flash memory system of claim 20, wherein said one or more read values for said plurality of bits are converted to the reliability value using a distribution marginalization.

30. The flash memory system of claim 29, wherein said distribution marginalization computes the reliability value for said given bit given that a first pattern was read, wherein said reliability value for said given bit is based on multiple probabilities for different patterns that were written given that said first pattern was read.