Apparatus and method to manage high capacity storage devices

• US 9,292,379 B2
• Filed: 09/28/2013
• Issued: 03/22/2016
• Est. Priority Date: 09/28/2013
• Status: Active Grant

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Grimsrud, Knut, Khan, Jawad, Mangold, Richard
• Primary Examiner(s): Merant, Guerrier
• Application Number:
  US14/040,651
• Publication Number:
  US 20150095737A1
• Time in Patent Office: 906 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1004 to protect a block of data words, e.g. CRC or checksum G06F11/1076 takes precedence; security arrangements for protecting computers or computer systems against unauthorized activity G06F21/00
• CPC Class Codes: G06F 11/1016 Error in accessing a memory location, i.e. addressing error

Abstract

Apparatus, systems, and methods to manage high capacity memory devices are described. In one example, a controller comprises logic to receive a write operation comprising payload data, a namespace identifier (ID) and a first extended logical block address (LBA), compute a first system cyclic redundancy check (CRC) using a payload CRC, the namespace ID and the first extended LBA, store the first system CRC in association with the first extended LBA in a local memory, and write the payload data, the first system CRC, and a truncated LBA derived from the first extended LBA to a memory. Other examples are also disclosed and claimed.

Claims

1. A controller comprising logic to:

receive a write operation comprising payload data, a namespace identifier (ID) and a first extended logical block address (LBA);

compute a first system cyclic redundancy check (CRC) by applying an XOR operation to a payload CRC data, the namespace ID and the first extended LBA;

store the first system CRC in association with the first extended LBA in a first local memory;

generate a truncated LBA from the extended LBA by dropping one or more least significant bits from the extended LBA;

write the payload data, the first system CRC, and a truncated LBA derived from the first extended LBA to a second memory, separate from the first local memory; and

fill a memory space on the second memory for the one or more least significant bits with one or more ECC parity bits.

2. The controller of claim 1, wherein:

the first extended LBA maps to a data sector on the memory;

the memory is mapped into blocks which contain eight data sectors; and

the truncated LBA written to the memory omits the three least significant bits of the first extended LBA.

3. The controller of claim 2, wherein:

the first extended LBA maps to a data sector that measures between 512 bytes and 528 bytes; and

the memory is mapped into blocks that measure approximately 4 kilobytes.

4. The controller of claim 1, further comprising logic to

receive a read operation comprising the first extended LBA;

retrieve the payload data, the first system CRC, and the truncated LBA from the memory; and

determine a second extended LBA from the truncated LBA.

5. The controller of claim 4, further comprising logic to:

compute a second system cyclic redundancy check (CRC) value using the payload data, the namespace ID and the second extended LBA; and

implement an error routine when the second system CRC does not match the first system CRC.

6. The controller of claim 4, further comprising logic to:

compute a second system cyclic redundancy check (CRC) value using a payload data, the namespace ID and the second extended LBA; and

return the payload data when the second system CRC matches the first system CRC.

7. An apparatus, comprising:

a non-volatile memory; and

a controller coupled to the memory and comprising logic to;

receive a write operation comprising payload data, a namespace identifier (ID) and a first extended logical block address (LBA);

compute a first system cyclic redundancy check (CRC) by applying an XOR operation to a payload CRC data, the namespace ID and the first extended LBA;

store the first system CRC in association with the first extended LBA in a local memory;

generate a truncated LBA from the extended LBA by dropping one or more least significant bits from the extended LBA;

write the payload data, the first system CRC, and a truncated LBA derived from the first extended LBA to a second memory, separate from the first local memory; and

fill a memory space on the second memory for the one or more least significant bits with one or more ECC parity bits.

8. The apparatus of claim 7, wherein:

the first extended LBA maps to a data sector on the memory;

the memory is mapped into blocks which contain eight data sectors; and

the truncated LBA written to the memory omits the three least significant bits of the first extended LBA.

9. The apparatus of claim 8, wherein:

the first extended LBA maps to a data sector that measures between 512 bytes and 528 bytes; and

the memory is mapped into blocks that measure approximately 4 kilobytes.

10. The apparatus of claim 7, further comprising logic to

receive a read operation comprising the first extended LBA;

retrieve the payload data, the first system CRC, and the truncated LBA from the memory; and

determine a second extended LBA from the truncated LBA.

11. The apparatus of claim 10, further comprising logic to:

compute a second system cyclic redundancy check (CRC) value using the payload data, the namespace ID and the second extended LBA; and

implement an error routine when the second system CRC does not match the first system CRC.

12. The apparatus of claim 10, further comprising logic to:

compute a second system cyclic redundancy check (CRC) value using a payload data, the namespace ID and the second extended LBA; and

return the payload data when the second system CRC matches the first system CRC.

13. An electronic device, comprising:

at least one processor; and

at least one memory device comprising a memory; and

a controller coupled to the memory and comprising logic to;

receive a write operation comprising payload data, a namespace identifier (ID) and a first extended logical block address (LBA);

compute a first system cyclic redundancy check (CRC) by applying an XOR operation to a payload CRC data, the namespace ID and the first extended LBA;

store the first system CRC in association with the first extended LBA in a local memory;

generate a truncated LBA from the extended LBA by dropping one or more least significant bits from the extended LBA;

write the payload data, the first system CRC, and a truncated LBA derived from the first extended LBA to a second memory, separate from the first local memory; and

fill a memory space on the second memory for the one or more least significant bits with one or more ECC parity bits.

14. The electronic device of claim 13, wherein:

the first extended LBA maps to a data sector on the memory;

the memory is mapped into blocks which contain eight data sectors; and

the truncated LBA written to the memory omits the three least significant bits of the first extended LBA.

15. The electronic device of claim 14, wherein:

the first extended LBA maps to a data sector that measures between 512 bytes and 528 bytes; and

the memory is mapped into blocks that measure approximately 4 kilobytes.

16. The electronic device of claim 13, further comprising logic to

receive a read operation comprising the first extended LBA;

retrieve the payload data, the first system CRC, and the truncated LBA from the memory; and

determine a second extended LBA from the truncated LBA.

17. The electronic device of claim 16, further comprising logic to:

compute a second system cyclic redundancy check (CRC) value using the payload data, the namespace ID and the second extended LBA; and

implement an error routine when the second system CRC does not match the first system CRC.

18. The electronic device of claim 16, further comprising logic to:

compute a second system cyclic redundancy check (CRC) value using a payload data, the namespace ID and the second extended LBA; and

return the payload data when the second system CRC matches the first system CRC.