Memory system

• US 9,292,428 B2
• Filed: 01/31/2013
• Issued: 03/22/2016
• Est. Priority Date: 09/05/2012
• Status: Expired due to Fees

• Current Assignee: Toshiba Memory Corporation (Kioxia Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Kanamori, Yuki, Miyake, Yusuke
• Primary Examiner(s): Queler, Adam M
• Assistant Examiner(s): Bone, Dustin
• Application Number:
  US13/755,133
• Publication Number:
  US 20140068149A1
• Time in Patent Office: 1,146 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 7/58 Random or pseudo-random number generators
• CPC Class Codes: G11C 11/5628 Programming or writing circuits; Data input circuits
• CPC Class Codes: G11C 16/3495 Circuits or methods to detect or delay wearout of nonvolatile EPROM or EEPROM memory devices, e.g. by counting numbers of erase or reprogram cycles, by using multiple memory areas serially or cyclically
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor

Abstract

According to one embodiment, a memory system includes a nonvolatile semiconductor storage device, a first storage module, a second storage module, a controller, a random number generator, and a randomizing module. The first storage module stores a plurality of management data. The second storage module stores seed data. The controller issues a first command to designate one of the management data, and issues a second command to command writing in or reading from the storage device. The random number generator generates random number data, by shuffling the seed data, based on the management data that is designated by the first command. The randomizing module randomizes written data or read data, based on the random number data.

Claims

1. A memory system comprising:

a nonvolatile semiconductor storage device including a nonvolatile semiconductor memory;

a volatile memory in which a plurality of management data to manage writing in or reading from the nonvolatile semiconductor storage device is stored;

a controller that issues a first command to designate first management data stored in the volatile memory, and that issues a second command to designate writing in or reading from the nonvolatile semiconductor storage device; and

a circuit,

wherein the nonvolatile semiconductor storage device includes;

a first module that generates first random number data by shuffling first seed data based on the first management data designated by the first command,

a second module that randomizes write data into first data based on the first random number data, the write data corresponding to the second command to designate writing in the nonvolatile semiconductor storage device, and

a third module that recovers second data into read data using the first random number data, the second data being stored in the nonvolatile semiconductor memory, and the read data corresponding to the second command to designate read from the nonvolatile semiconductor device,

the circuit inverts the data randomized by the second module for each page, based on the first command,

the nonvolatile semiconductor memory is formed of a plurality of pages, to store a plurality of bits of data in one memory cell,

the nonvolatile semiconductor memory includes at least a lower page and an upper page,

the circuit inverts data of one of the lower page and the upper page, based on the second data, and

the second data is number of erases, and the circuit inverts data of the lower page when the number of erases is an odd number, and inverts data of the upper page when the number of erases is an even number.

2. The memory system according to claim 1, wherein the controller issues the second command after the first command is issued.

3. The memory system according to claim 1, wherein the controller issues the first command after the second command is issued.

4. The memory system according to claim 1, wherein

the second module includes an exclusive-OR gate which is supplied with the random number data and the write data, and the third module includes an exclusive-OR gate which is supplied with the random number and the read data.

5. The memory system according to claim 1, wherein

the management data are one of number of erases the nonvolatile semiconductor storage device, number of reads from the nonvolatile semiconductor storage device, temperature information, time information, logical address, physical address, and cumulative sector value which indicates number of sectors.

12. The memory system according to claim 1, wherein

the first and second commands are part of a command sequence received by the nonvolatile semiconductor storage device.

13. The memory system according to claim 1, wherein

the nonvolatile semiconductor memory includes a plurality of blocks which include the pages, and

the first data is set to a value which equalizes an average threshold level of each memory cell, when a block of the nonvolatile semiconductor memory is repeatedly used.

6. A memory system comprising:

a first module;

a controller;

a second module that generates random number data based on first data that is stored in the first module and second data to manage writing or reading of data that is designated by a command from the controller, that randomizes write data based on the random number data, and that recovers read data based on the random number data; and

a third circuit, wherein

the command is sent from the controller to the first module,

the second module includes;

a first circuit which generates the random number data, based on seed data serving as the first data and management data serving as the second data, and

a second circuit which randomizes the write data or the read data based on the random number data generated by the first circuit,

the first module is formed of a plurality of pages, to store a plurality of bits of data in one memory cell,

the third circuit inverts the data randomized by the second circuit for each page, based on a first command,

the first module includes at least a lower page and an upper page,

the third circuit inverts data of one of the lower page and the upper page based on the second data, and

the second data is number of erases, and the third circuit inverts data of the lower page when the number of erases is an odd number, and inverts data of the upper page when the number of erases is an even number.

7. The memory system according to claim 6, wherein the first data is seed data to generate the random number data.

8. The memory system according to claim 6, wherein

the command is a command sequence that includes the first command to designate one of the first data, and a second command to command writing in or reading from the first module.

9. The memory system according to claim 8, wherein

the controller issues the second command after the first command is issued.

10. The memory system according to claim 8, wherein

the controller issues the first command after the second command is issued.

11. The memory system according to claim 6, wherein

the first module includes a plurality of blocks which include the pages, and

the first data is set to a value which equalizes an average threshold level of each memory cell, when a block of the first module is repeatedly used.

14. The memory system according to claim 6, wherein

the first command is part of a command sequence that also includes a second command, the command sequence being received by the nonvolatile semiconductor storage device.