Memory device, host device, and sampling clock adjusting method

• US 9,292,433 B2
• Filed: 08/12/2014
• Issued: 03/22/2016
• Est. Priority Date: 12/26/2008
• Status: Active Grant

• Current Assignee: Kioxia Corporation
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Fujimoto, Akihisa
• Primary Examiner(s): Abbaszadeh, Jaweed A
• Assistant Examiner(s): Chen, Xuxing
• Application Number:
  US14/458,012
• Publication Number:
  US 20140351499A1
• Time in Patent Office: 588 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 1/12 Synchronisation of different clock signals provided by a plurality of clock generators
• CPC Class Codes: G06F 12/0246 in block erasable memory, e.g. flash memory
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

A memory card includes a memory controller configured to perform control for sending and receiving a command signal, a response signal, a data signal, and a status signal in synchronization with a clock signal, and a memory-side pattern signal storage unit configured to store a tuning pattern signal to be sent to a host device. The tuning pattern signal is used by the host device to adjust the phase of the clock signal for use as a sampling clock signal. The memory card sends a first tuning pattern signal through a command line and a second tuning pattern signal through a data line concurrently.

Claims

1. A sampling clock adjusting method for a host device connected to a memory device including a nonvolatile semiconductor memory unit through signal lines, the host device including a host controller, a sampling clock adjustment unit, and a clock unit configured to generate a clock signal, the method comprising:

setting, by the sampling clock adjustment unit, an initial value of a phase of a sampling clock signal determining a sampling point at which the host device receives a signal from the memory device on the basis of a phase of the clock signal, wherein the host controller performs control to send a command signal through a command line, receive a response signal through the command line, send and receive a data signal through data lines, and send a clock signal through a clock line, and wherein the memory device sends the signal in synchronization with the clock signal received from the host device;

sending, by the host device, a tuning command to the memory device through the command line;

sending, by the memory device upon receiving the tuning command, a first tuning signal and a second tuning signal for adjusting the phase of the sampling clock signal, wherein a pattern of the first tuning signal and a pattern of the second tuning signal are prestored in a memory device side signal pattern storage, and wherein the first tuning signal is sent through a first signal line, the second tuning signal is sent through a second signal line, and a time period during which the first tuning signal is sent and a time period during which the second tuning signal is sent overlap each other;

receiving, by the host device, the first tuning signal and the second tuning signal; and

comparing, by the host controller, patterns of the first tuning signal and the second tuning signal received with patterns of the first tuning signal and the second tuning signal prestored in a host side signal pattern storage, and adjusting, by the sampling clock adjustment unit, the phase of the sampling clock signal to an optimum sampling point based on a result of the comparison.

2. The sampling clock adjusting method according to claim 1, wherein the sampling clock adjustment unit generates a plurality of oversampling clock signals whose phases are different, and uses one oversampling clock signal selected from the plurality of oversampling clock signals as the sampling signal after phase adjustment.

3. The sampling clock adjusting method according to claim 1, wherein the sampling clock adjustment unit repeats the sampling clock phase adjustment at least until patterns are matched between sampled patterns and stored patterns in the host.

4. The sampling clock adjusting method according to claim 1, wherein the sampling clock adjustment unit generates a sampling clock signal whose phases can be shifted and repeats tuning of the sampling clock signal by shifting phase and selects one of phases from the plurality of tuning results and uses a selected phase as the phase of sampling clock signal.

5. The sampling clock adjusting method according to claim 1, wherein the host controller changes sending and receiving conditions of the signals based on a result of the comparison.

6. The sampling clock adjusting method according to claim 5, wherein the sending and receiving conditions include frequency of the clock signal and the sampling clock signal.

7. The sampling clock adjusting method according to claim 1, wherein the nonvolatile semiconductor memory of the memory device is a NAND flash memory unit.

8. The sampling clock adjusting method according to claim 1, wherein the memory device is a memory card.