Multi-granular cache management in multi-processor computing environments
First Claim
1. A method for cache management in a multi-processor computing environment, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the cache associated with a directory having a number of directory entries and further associated with a side table having a smaller number of side table entries, the method comprising:
- identifying a first cache line associated with a first directory entry, the first directory entry associating the first cache line with a tag and a set of full-line descriptive bits, the first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity;
creating a side table entry for the first cache line, the side table entry associating the tag with at least one set of sub-line descriptive bits, each set of sub-line descriptive bits associated with a sub-cache line portion of the first cache line, wherein the creating places the first cache line a sub-line coherency mode, and wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode;
identifying an operation in the computing environment, the operation accessing a memory address within a second cache line associated with a second directory entry, the second directory entry associating the second cache line with a second tag and a second set of full-line descriptive bits;
locating the second tag in the side table;
based on the locating, determining that the second cache line is in the sub-line coherency mode; and
based on the determining, accessing and managing only a first sub-cache line portion of the second cache line while performing the operation, the first sub-cache line portion associated with the memory address.
1 Assignment
0 Petitions
Accused Products
Abstract
Cache lines in a multi-processor computing environment are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. Each cache is associated with a directory having a number of directory entries and with a side table having a smaller number of entries. The directory entry for a cache line associates the cache line with a tag and a set of full-line descriptive bits. Creating a side table entry for the cache line places the cache line in sub-line coherency mode. The side table entry associates each of the sub-cache line portions of the cache line with a set of sub-line descriptive bits. Removing the side table entry may return the cache line to full-line coherency mode.
38 Citations
17 Claims
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1. A method for cache management in a multi-processor computing environment, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the cache associated with a directory having a number of directory entries and further associated with a side table having a smaller number of side table entries, the method comprising:
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identifying a first cache line associated with a first directory entry, the first directory entry associating the first cache line with a tag and a set of full-line descriptive bits, the first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity; creating a side table entry for the first cache line, the side table entry associating the tag with at least one set of sub-line descriptive bits, each set of sub-line descriptive bits associated with a sub-cache line portion of the first cache line, wherein the creating places the first cache line a sub-line coherency mode, and wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; identifying an operation in the computing environment, the operation accessing a memory address within a second cache line associated with a second directory entry, the second directory entry associating the second cache line with a second tag and a second set of full-line descriptive bits; locating the second tag in the side table; based on the locating, determining that the second cache line is in the sub-line coherency mode; and based on the determining, accessing and managing only a first sub-cache line portion of the second cache line while performing the operation, the first sub-cache line portion associated with the memory address. - View Dependent Claims (2, 3, 4, 5)
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6. A computer system for cache management in a multi-processor computing environment, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the cache associated with a directory having a number of directory entries and further associated with a side table having a smaller number of side table entries, the computer system comprising:
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a memory; and a processor in communication with the memory, wherein the computer system is configured to perform a method, the method comprising; identifying a first cache line associated with a first directory entry, the first directory entry associating the first cache line with a tag and a set of full-line descriptive bits, the first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity; creating a side table entry for the first cache line, the side table entry associating the tag with at least one set of sub-line descriptive bits, each set of sub-line descriptive bits associated with a sub-cache line portion of the first cache line, wherein the creating places the first cache line a sub-line coherency mode, and wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; identifying an operation in the computing environment, the operation accessing a memory address within a second cache line associated with a second directory entry, the second directory entry associating the second cache line with a second tag and a second set of full-line descriptive bits; locating the second tag in the side table; based on the locating, determining that the second cache line is in the sub-line coherency mode; and based on the determining, accessing and managing only a first sub-cache line portion of the second cache line while performing the operation the first sub-cache line portion associated with the memory address. - View Dependent Claims (7, 8, 9, 10, 11, 12)
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13. A computer program product for cache management in a multi-processor computing environment, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the cache associated with a directory having a number of directory entries and further associated with a side table having a smaller number of side table entries, the computer program product comprising:
a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method, the method comprising; identifying a first cache line associated with a first directory entry, the first directory entry associating the first cache line with a tag and a set of full-line descriptive bits, the first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity; creating a side table entry for the first cache line, the side table entry associating the tag with at least one set of sub-line descriptive bits, each set of sub-line descriptive bits associated with a sub-cache line portion of the first cache line, wherein the creating places the first cache line a sub-line coherency mode, and wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; identifying an operation in the computing environment, the operation accessing a memory address within a second cache line associated with a second directory entry, the second directory entry associating the second cache line with a second tag and a second set of full-line descriptive bits; locating the second tag in the side table; based on the locating, determining that the second cache line is in the sub-line coherency mode; and based on the determining, accessing and managing only a first sub-cache line portion of the second cache line while performing the operation, the first sub-cache line portion associated with the memory address. - View Dependent Claims (14, 15, 16, 17)
Specification