Configurable bandwidth memory devices and methods

• US 9,293,170 B2
• Filed: 12/20/2013
• Issued: 03/22/2016
• Est. Priority Date: 03/23/2009
• Status: Active Grant

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Jeddeloh, Joe M.
• Primary Examiner(s): AUDUONG, GENE NGHIA
• Application Number:
  US14/136,925
• Publication Number:
  US 20140112046A1
• Time in Patent Office: 823 Days
• Field of Search: 365/51, 365/52, 365/63, 365/189.05, 365/191
• US Class Current: 1/1
• CPC Class Codes: G06F 13/4234 being a memory bus
• CPC Class Codes: G11C 11/4093 Input/output [I/O] data interface arrangements, e.g. data buffers
• CPC Class Codes: G11C 5/02 Disposition of storage elements, e.g. in the form of a matrix array
• CPC Class Codes: G11C 5/063 Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Memory devices and methods are described, such as those that include a stack of memory dies and an attached logic die. Method and devices described provide for configuring bandwidth for selected portions of a stack of memory dies. Additional devices, systems, and methods are disclosed.

Claims

1. A memory device, comprising:

a stack of memory dies, including a number of memory portions;

a logic die coupled to the stack of memory dies;

a memory fabric control register selectably coupled to the number of memory portions to select a number of memory portions that operate synchronously for a single memory request;

wherein each memory portion includes both a direct connection to an originating and/or destination device, and a buffered connection to the originating and/or destination device.

2. The memory device of claim 1, wherein the logic die is located apart from the stack of memory dies.

3. The memory device of claim 1, wherein the logic die is stacked with the stack of memory dies.

4. The memory device of claim 1, wherein the memory portions include memory vaults.

5. A memory device, comprising:

a stack of memory dies, including a number of memory portions;

a logic die coupled to the stack of memory dies;

a memory fabric control register selectably coupled to the number of memory portions to select a number of memory portions that operate synchronously for a single memory request;

a number of direct connections, and a buffered connection between an originating and/or destination device and the stack of memory dies.

6. The memory device of claim 5, wherein each memory portion includes both a direct connection to the originating and/or destination device, and a buffered connection to the originating and/or destination device.

7. The memory device of claim 5, wherein the fabric control register is adapted to configure bandwidth in the memory device upon reset of the memory device.

8. The memory device of claim 5, wherein the fabric control register is adapted to configure bandwidth in the memory device upon startup of the memory device.

9. The memory device of claim 5, wherein the memory portions include memory vaults.

10. A system, comprising:

a stack of memory dies, including a number of memory portions;

a logic die coupled to the stack of memory dies;

a memory fabric control register selectably coupled to the number of memory portions to select a number of memory portions that operate synchronously for a single memory request;

wherein each memory portion includes both a direct connection to the originating and/or destination device, and a buffered connection to the originating and/or destination device;

a processor coupled to the stack of memory dies through a bus;

a display device; and

a controller to input information to the system.

11. The system of claim 10, wherein the logic die is located apart from the stack of memory dies.

12. The system of claim 10, wherein the logic die is stacked with the stack of memory dies.

13. The system of claim 10, wherein the memory portions include memory vaults.

14. The system of claim 10, wherein the system is configured as a laptop computer.

15. The system of claim 10, wherein the system is configured as a tablet computer.

16. The system of claim 10, wherein the system is configured as a desktop computer.