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SRAM cell with dynamic split ground and split wordline

  • US 9,293,192 B1
  • Filed: 12/02/2014
  • Issued: 03/22/2016
  • Est. Priority Date: 12/02/2014
  • Status: Active Grant
First Claim
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1. A memory cell, comprising:

  • a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline;

    a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline; and

    a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR), the GNDL being connected to a transistor of a first inverter of the cross coupled inverters and the GNDR being connected to a first transistor of a second inverter of the cross coupled inverters, andwherein during read access for the second bitline, the GNDL is raised above common GND and/or GNDR is lowered below GND.

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