SRAM cell with dynamic split ground and split wordline
First Claim
1. A memory cell, comprising:
- a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline;
a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline; and
a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR), the GNDL being connected to a transistor of a first inverter of the cross coupled inverters and the GNDR being connected to a first transistor of a second inverter of the cross coupled inverters, andwherein during read access for the second bitline, the GNDL is raised above common GND and/or GNDR is lowered below GND.
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Accused Products
Abstract
An SRAM cell with dynamic split ground (GND) and split wordline (WL) for extreme scaling is disclosed. The memory cell includes a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline. The memory cell further includes a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline. The memory cell further includes a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR). The GNDL is connected to a transistor of a first inverter of the cross coupled inverters and the GNDR is connected to a first transistor of a second inverter of the cross coupled inverters.
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Citations
16 Claims
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1. A memory cell, comprising:
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a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline; a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline; and a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR), the GNDL being connected to a transistor of a first inverter of the cross coupled inverters and the GNDR being connected to a first transistor of a second inverter of the cross coupled inverters, and wherein during read access for the second bitline, the GNDL is raised above common GND and/or GNDR is lowered below GND. - View Dependent Claims (2, 3, 4, 5, 6, 7, 11, 12)
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8. A memory cell, comprising:
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a first access transistor enabled by a first wordline to control access to cross coupled inverters by a first bitline; a second access transistor enabled by a second wordline to control access to the cross coupled inverters by a second bitline; and a split ground line comprising a first ground line (GNDL) separated from a second ground line (GNDR), the GNDL being connected to a transistor of a first inverter of the cross coupled inverters and the GNDR being connected to a first transistor of a second inverter of the cross coupled inverters, wherein during read access of first bitline on BL for, the GNDR is raised by about 10% of Vdd above common ground GND and/or GNDL is lowered by about 10% of Vdd below GND. - View Dependent Claims (9, 10)
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13. A memory cell, comprising:
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cross coupled inverters comprising PFETs and NFETs; a bitline left (BL) which accesses a first inverter of cross coupled inverters by enabling a first access transistor; a bitline right (BR) which accesses a second inverter of the cross coupled inverters by enabling a second access transistor; a wordline left (WL) with enables the first access transistor; a wordline right (WR) which enables the second access transistor; and a split vertical ground line comprising a first vertical ground line (GNDL) separated from a second vertical ground line (GNDR), the GNDL being connected to the first inverter of the cross coupled inverters and the GNDR being connected to the second inverter of the cross coupled inverters, wherein; during global reset of memory array to zero state, the GNDL is raised to Vdd to pull down CR and push up CL; during global set of memory array to one state, the GNDR is raised to Vdd to pull down the CL and push up the CR; during global set/reset of specific columns of memory array to specific zero state and one state, the GNDL of specific columns are raised to Vdd, and the GNDR of other specific columns are raised to Vdd; the GNDL is connected directly to an NFET of the first inverter; and the GNDR is connected directly to an NFET of the second inverter. - View Dependent Claims (14, 15, 16)
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Specification