Programming of gated phase-change memory cells
First Claim
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1. A method for programming gated phase-change memory cells, each with a gate, source and drain, having s≧
- 2 programmable cell-states including an amorphous RESET state and at least one crystalline state, the method comprising;
reading a memory cell to be programmed, before programming, to obtain an indication of cell-state;
applying a programming signal between the source and drain of the memory cell to program the cell to a desired cell-state; and
only when programming the cell from a crystalline state to the RESET state, as determined by indicating the crystalline state from the reading of the cell, applying a bias voltage to the gate of the cell to increase the cell resistance; and
reprogramming the cell in the amorphous RESET state to the RESET state, as determined by indicating the amorphous RESET state from the reading of the cell, wherein the bias voltage is not applied to the gate of the cell at any time during the reprogramming, and wherein the reprogramming includes applying the programming signal between the source and drain of the memory cell to reprogram the cell to the RESET state while there is no voltage applied to the gate of the cell.
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Abstract
A method for programming gated phase-change memory cells, each with a gate, source and drain, having s≧2 programmable cell-states including an amorphous RESET state and at least one crystalline state includes applying a programming signal between the source and drain of a memory cell to program that cell to a desired cell-state; and when programming the cell from a crystalline state to the RESET state, applying a bias voltage to the gate of the cell to increase the cell resistance.
27 Citations
20 Claims
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1. A method for programming gated phase-change memory cells, each with a gate, source and drain, having s≧
- 2 programmable cell-states including an amorphous RESET state and at least one crystalline state, the method comprising;
reading a memory cell to be programmed, before programming, to obtain an indication of cell-state; applying a programming signal between the source and drain of the memory cell to program the cell to a desired cell-state; and only when programming the cell from a crystalline state to the RESET state, as determined by indicating the crystalline state from the reading of the cell, applying a bias voltage to the gate of the cell to increase the cell resistance; and reprogramming the cell in the amorphous RESET state to the RESET state, as determined by indicating the amorphous RESET state from the reading of the cell, wherein the bias voltage is not applied to the gate of the cell at any time during the reprogramming, and wherein the reprogramming includes applying the programming signal between the source and drain of the memory cell to reprogram the cell to the RESET state while there is no voltage applied to the gate of the cell. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
- 2 programmable cell-states including an amorphous RESET state and at least one crystalline state, the method comprising;
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11. An apparatus for programming gated phase-change memory cells, each with a gate, source and drain, having s≧
- 2 programmable cell-states including an amorphous RESET state and at least one crystalline state, the apparatus comprising;
a signal generator configured to apply a programming signal between the source and drain of a memory cell to program the cell to a desired cell-state; the signal generator further configured to apply a read signal between the source and drain of each cell to facilitate making a read measurement to obtain an indication of cell-state; a current detector configured to measure cell current to obtain the cell-state; a bias voltage generator configured to apply a bias voltage to the gate of a cell; and a controller configured to control the signal generator and bias voltage generator such that, when programming a cell from a crystalline state to the RESET state, the bias voltage generator applies a bias voltage to the gate of the cell to increase the cell resistance, only when the read measurement has indicated that the cell is in the crystalline state prior to the programming, and when reprogramming the cell in the amorphous RESET state to the RESET state, as determined by indicating the amorphous RESET state from the reading of the cell, the bias voltage generator does not apply a bias voltage to the gate of the cell at any time during the reprogramming, and wherein the reprogramming includes applying the programming signal between the source and drain of the memory cell to reprogram the cell to the RESET state while there is no voltage applied to the gate of the cell. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
- 2 programmable cell-states including an amorphous RESET state and at least one crystalline state, the apparatus comprising;
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Current AssigneeInternational Business Machines Corporation
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Original AssigneeInternational Business Machines Corporation
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InventorsKrebs, Daniel
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Primary Examiner(s)Hoang, Huan
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Assistant Examiner(s)Huerta, Pablo
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Application NumberUS13/900,178Publication NumberTime in Patent Office1,035 DaysField of Search365/163US Class Current1/1CPC Class CodesG11C 11/5678 using amorphous/crystalline...G11C 13/0004 comprising amorphous/crysta...G11C 13/0009 RRAM elements whose operati...G11C 13/004 Reading or sensing circuits...G11C 13/0069 Writing or programming circ...G11C 2013/0071 Write using write potential...G11C 2013/0076 Write operation performed d...G11C 2213/53 Structure wherein the resis...H10B 63/30 comprising selection compon...H10N 70/231 based on solid-state phase ...H10N 70/253 having three or more termin...H10N 70/823 adapted for essentially hor...
