Selectively grown self-aligned fins for deep isolation integration

• US 9,293,375 B2
• Filed: 04/24/2014
• Issued: 03/22/2016
• Est. Priority Date: 04/24/2014
• Status: Expired due to Fees

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Petrarca, Kevin S., Sieg, Stuart A., Standaert, Theodorus E.
• Primary Examiner(s): Weiss, Howard
• Application Number:
  US14/260,724
• Publication Number:
  US 20150311121A1
• Time in Patent Office: 698 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02123 the material containing silicon
• CPC Class Codes: H01L 21/0337 characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
• CPC Class Codes: H01L 21/30604 Chemical etching
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/31051 Planarisation of the insulating layers H01L21/31058 takes precedence
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/31144 using masks
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: H01L 21/823431 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 21/823481 isolation region manufacturing related aspects, e.g. to avoid interaction of isolation region with adjacent structure
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions
• CPC Class Codes: H01L 29/6656 using multiple spacer layers, e.g. multiple sidewall spacers
• CPC Class Codes: H01L 29/66795 with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/785 having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET

Abstract

A trench isolation structure is formed beneath a topmost surface of a semiconductor substrate. A mandrel structure having a bottommost surface that straddles a sidewall edge of the underlying trench isolation structure is then formed. Nitride spacers are formed on sidewalls of the mandrel structure and thereafter the mandrel structure is removed. A dielectric oxide material is then formed having a topmost surface that is coplanar with a topmost surface of each remaining nitride spacer. Each nitride spacer is removed and thereafter a semiconductor fin is epitaxially grown within a cavity in the dielectric oxide material which exposes a topmost surface of the semiconductor substrate.

Claims

1. A method of forming a semiconductor structure, said method comprising:

providing a trench isolation structure in a semiconductor substrate;

forming a mandrel structure having a first portion located above said semiconductor substrate and a second portion located above said trench isolation structure, wherein a bottommost surface of said mandrel structure straddles a sidewall edge of said trench isolation structure;

forming a nitride spacer on each sidewall of said mandrel structure;

removing said mandrel structure selective to said nitride spacers;

forming a dielectric oxide material having a topmost surface that is coplanar with a topmost surface of said nitride spacers;

removing one of nitride spacers to provide a cavity exposing a portion of a topmost surface of said semiconductor substrate and another of said nitride spacers to provide another cavity exposing a portion of a topmost surface of said trench isolation structure; and

epitaxially growing a semiconductor fin in said cavity that exposes said portion of said topmost surface of said semiconductor substrate, but not in said another cavity that exposes said portion of said topmost surface of said trench isolation structure, wherein a bottommost surface of said semiconductor fin directly contacts an exposed portion of said topmost surface of said semiconductor substrate.

2. The method of claim 1, wherein said providing said trench isolation structure in said semiconductor substrate comprises:

forming a hard mask material stack on said topmost surface of said semiconductor substrate;

forming a patterned photoresist on a topmost surface of said hard mask material stack;

etching an opening entirely through said hard mask material stack and partially through said semiconductor substrate;

depositing a trench dielectric oxide material in said opening and on said topmost surface of said hard mask material stack; and

removing said trench dielectric oxide material on said topmost surface of said hard mask material stack by planarization.

3. The method of claim 2, wherein said hard mask stack comprises, from bottom to top, an oxide hard mask layer and a nitride hard mask layer, and remaining portions of said nitride hard mask layer that are provided after etching said opening serve as an planarization stop layer.

4. The method of claim 3, wherein said remaining portions of said nitride hard mask layer are removed after said planarization to expose remaining portions of said oxide hard mask layer.

5. The method of claim 4, further comprising forming a screen oxide layer directly on a topmost surface of each remaining portion of said oxide hard mask layer and directly on said topmost surface of said trench isolation structure.

6. The method of claim 5, wherein said bottommost surface of said mandrel structure is located on said screen oxide layer.

7. The method of claim 1, wherein said forming said mandrel structure comprises:

depositing a layer of mandrel material; and

patterning said layer of mandrel material by lithography and etching.

8. The method of claim 7, wherein said layer of mandrel material comprises amorphous silicon.

9. The method of claim 7, wherein said layer of mandrel material comprises an organic self-planarizing material.

10. The method of claim 1, wherein said forming said nitride spacer on each sidewall of said mandrel structure comprises:

depositing a nitride dielectric material; and

etching said nitride dielectric material.

11. The method of claim 1, wherein said removing said mandrel structure selective to said nitride spacers comprises an anisotropic etch.

12. The method of claim 1, wherein said forming said dielectric oxide material having said topmost surface that is coplanar with said topmost surface of said nitride spacers comprises;

depositing said dielectric oxide material; and

removing portions of said dielectric oxide material that are disposed atop said nitride spacers by planarization.

13. The method of claim 1, wherein said semiconductor fin comprise a same semiconductor material as said semiconductor substrate.

14. The method of claim 1, wherein said semiconductor fin comprise a different semiconductor material as said semiconductor substrate.

15. The method of claim 1, further comprises filling said another cavity with another dielectric oxide material.

20. The method of claim 1, wherein said bottommost surface of said semiconductor fin is located beneath said topmost surface of said trench isolation structure.

16. A method of forming a semiconductor structure, said method comprising:

providing a structure including a hard mask material stack comprising from bottom to top, an oxide hard mask layer and a nitride hard mask layer on a topmost surface of a semiconductor substrate;

forming an opening entirely through said hard mask material stack and partially through said semiconductor substrate;

providing a trench isolation structure in said opening, wherein said trench isolation structure has a topmost surface that is coplanar with a topmost surface of remaining portions of said nitride hard mask layer;

removing said remaining portion of said nitride hard mask layer to expose remaining portions of said oxide hard mask layer;

forming a screen oxide layer on each of said remaining portions of said oxide hard mask layer and said topmost surface of said trench isolation structure;

forming a mandrel structure on said screen oxide layer and having a first portion located above said semiconductor substrate and a second portion located above said trench isolation structure, wherein a bottommost surface of said mandrel structure straddles a sidewall edge of said trench isolation structure;

forming a nitride spacer on each sidewall of said mandrel structure;

removing said mandrel structure selective to said nitride spacers;

forming a dielectric oxide material having a topmost surface that is coplanar with a topmost surface of said nitride spacers;

removing one of nitride spacers to provide a cavity exposing a portion of said screen oxide layer located above said topmost surface of said semiconductor substrate and another of said nitride spacers to provide another cavity exposing another portion of said screen oxide layer located above said topmost surface of said trench isolation structure;

extending said cavity to expose said topmost surface of said semiconductor substrate, and said another cavity to expose said topmost surface of said trench isolation structure; and

epitaxially growing a semiconductor fin in said cavity that exposes said portion of said topmost surface of said semiconductor substrate, but not in said another cavity that exposes said portion of said topmost surface of said trench isolation structure, wherein a bottommost surface of said semiconductor fin directly contacts an exposed portion of said topmost surface of said semiconductor substrate.

17. The method of claim 16, wherein said forming said opening entirely through said hard mask material stack and partially through said semiconductor substrate comprises lithography and etching.

18. The method of claim 16, wherein said forming said mandrel structure comprises:

depositing a layer of mandrel material; and

patterning said layer of mandrel material by lithography and etching.

19. The method of claim 16, further comprises filling said another cavity with another dielectric oxide material.