Apparatus and method for power MOS transistor

• US 9,293,376 B2
• Filed: 07/11/2012
• Issued: 03/22/2016
• Est. Priority Date: 07/11/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Su, Po-Chih, Chou, Hsueh-Liang, Ng, Chun-Wai, Liu, Ruey-Hsin
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): JIANG, FANG-XING
• Application Number:
  US13/546,824
• Publication Number:
  US 20140015045A1
• Time in Patent Office: 1,350 Days
• Field of Search: 257331-338, 438/243
• US Class Current: 1/1
• CPC Class Codes: H01L 21/26586 characterised by the angle between the ion beam and the crystal planes or the main crystal surface
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 21/2815 part or whole of the electrode is a sidewall spacer or made by a similar technique, e.g. transformation under mask, plating
• CPC Class Codes: H01L 21/823456 gate conductors with different shapes, lengths or dimensions
• CPC Class Codes: H01L 21/823462 with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
• CPC Class Codes: H01L 21/823487 with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface with a current flow parallel to the substrate surface H01L21/823431
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 29/0886 Shape
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/40114 the electrodes comprising a conductor-insulator-conductor-insulator-semiconductor structure
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/42376 characterised by the length or the sectional shape
• CPC Class Codes: H01L 29/66734 with a step of recessing the gate electrode, e.g. to form a trench gate electrode
• CPC Class Codes: H01L 29/781 Inverted VDMOS transistors, i.e. Source-Down VDMOS transistors
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors
• CPC Class Codes: H01L 29/7835 with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs

Abstract

A power MOS transistor comprises a drain contact plug formed over a first side of a substrate, a source contact plug formed over a second side of the substrate and a trench formed between the first drain/source region and the second drain/source region. The trench comprises a first gate electrode, a second gate electrode, wherein top surfaces of the first gate electrode and the second gate electrode are aligned with a bottom surface of drain region. The trench further comprises a field plate formed between the first gate electrode and the second gate electrode, wherein the field plate is electrically coupled to the source region.

Claims

1. An apparatus comprising:

a first epitaxial layer over a first side of a substrate;

a second epitaxial layer over the first epitaxial layer;

a first drain/source contact plug formed over the second epitaxial layer, wherein the first drain/source contact plug is coupled to a first drain/source region, and wherein the first drain/source region is between the first drain/source contact plug and the second epitaxial layer;

a second drain/source contact plug formed below a second side of the substrate, wherein the second drain/source contact plug is coupled to a second drain/source region, and wherein the first side is opposite to the second side;

a trench formed in the first drain/source region, the second epitaxial layer and the first epitaxial layer, and extending from a top surface of the first drain/source region to a bottom portion of the first epitaxial layer, wherein a bottom surface of the trench is in direct contact with a top surface of the second drain/source region;

a gate electrode in a lower portion of the trench; and

a field plate surrounded by the gate electrode, wherein the field plate is electrically coupled to the second drain/source region, and wherein the second drain/source region is connected to the second drain/source contact plug through a low resistance path including the field plate.

2. The apparatus of claim 1, further comprising:

a drain drift region formed along sidewalls of a middle portion of the trench, wherein the trench is surrounded by the drain drift region.

3. The apparatus of claim 1, wherein:

the first epitaxial layer is a p-type epitaxial layer formed over the substrate, and wherein a bottom surface of the p-type epitaxial layer is in direct contact with a top surface of the substrate; and

a portion of a p+ region formed in the p-type epitaxial layer, wherein the p+ region is electrically coupled to the field plate, wherein a doping density of the p+ region is different from a doping density of the p-type epitaxial layer.

4. The apparatus of claim 3, wherein:

the second drain/source region is an n+ region formed between the gate electrode and the p+ region.

5. The apparatus of claim 4, wherein the n+ region is coupled to the second drain/source contact plug through the field plate, the p+ region and the substrate.

6. The apparatus of claim 1, further comprising:

a dielectric film formed between the gate electrode and the field plate.

7. The apparatus of claim 6, wherein:

the dielectric film is formed of an oxide and have a thickness in a range from about 0.1 um to about 0.5 um.

8. The apparatus of claim 1, wherein:

the first drain/source region is a drain of a trench power transistor; and

the second drain/source region is a source of the trench power transistor.

9. A device comprising:

a drain region formed over a substrate;

a source region formed over the substrate, wherein a bottom surface of the drain region is higher than a top surface of the source region; and

a trench formed in the drain region and epitaxial layers between the drain region and the substrate, and extending from the drain region to the source region;

a gate electrode in the trench; and

a field plate formed adjacent to the gate electrode, wherein the gate electrode and the field plate are separated by a dielectric film, and wherein the field plate is electrically coupled to and in direct contact with the source region.

10. The device of claim 9, further comprising:

a drain-drift region coupled to the drain region, wherein the trench is surrounded by the drain drift region.

11. The device of claim 9, further comprising:

a first epitaxial layer formed over the substrate, wherein a bottom surface of the first epitaxial layer is in direct contact with a top surface of the substrate; and

a second epitaxial layer formed over the first epitaxial layer, wherein a conductivity type of the second epitaxial layer is different from a conductivity type of the first epitaxial layer.

12. The device of claim 9, further comprising:

a drain contact plug coupled to the drain region, wherein the drain contact plug is formed over a first side of the substrate; and

a source contact plug coupled to the source region, wherein the source contact plug is formed over a second side of the substrate, wherein the second side is opposite to the first side.

13. A structure comprising:

a first epitaxial layer on a substrate;

a source region in the first epitaxial layer;

a second epitaxial layer on the first epitaxial layer;

a drain region in the second epitaxial layer over;

a trench formed in the drain region, the second epitaxial layer and the first epitaxial layer, and extending from the drain region to a bottom portion of the first epitaxial layer;

a gate electrode in the trench; and

a field plate adjacent to the gate electrode, wherein the gate electrode and the field plate are separated by a dielectric film, and wherein the field plate is electrically coupled to and in direct contact with the source region.

14. The structure of claim 13, further comprising:

a source contact plug underlying the substrate; and

a drain contact plug overlying the drain region.

15. The structure of claim 13, wherein:

the substrate is of a first conductivity type;

the first epitaxial layer is of the first conductivity type; and

the second epitaxial layer is of a second conductivity type.

16. The structure of claim 13, wherein:

the substrate is of a first conductivity type;

the source region is of a second conductivity type; and

the drain region is of the second conductivity type.

17. The structure of claim 13, further comprising:

a drain-drift region coupled to the drain region.