Electronic device and electronic apparatus

• US 9,293,483 B2
• Filed: 03/11/2015
• Issued: 03/22/2016
• Est. Priority Date: 04/27/1999
• Status: Expired due to Fees

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamauchi, Yukio, Fukunaga, Takeshi
• Primary Examiner(s): ABDIN, SHAHEDA A
• Application Number:
  US14/645,021
• Publication Number:
  US 20150187822A1
• Time in Patent Office: 377 Days
• US Class Current: 1/1
• CPC Class Codes: G09G 2300/0426 Layout of electrodes and connections
• CPC Class Codes: G09G 2300/0842 forming a memory circuit, e.g. a dynamic memory with one capacitor
• CPC Class Codes: G09G 2300/0861 with additional control of the display period without amending the charge stored in a pixel memory, e.g. by means of additional select electrodes
• CPC Class Codes: H01L 27/12 the substrate being other than a semiconductor body, e.g. an insulating body
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/124 with a particular composition, shape or layout of the wiring layers specially adapted to the circuit arrangement, e.g. scanning lines in LCD pixel circuits wiring structures per se H01L23/52
• CPC Class Codes: H01L 27/1251 comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs
• CPC Class Codes: H01L 27/1255 integrated with passive devices, e.g. auxiliary capacitors
• CPC Class Codes: H01L 27/13 combined with thin-film or thick-film passive components
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: H10K 2102/3026 Top emission
• CPC Class Codes: H10K 59/12 Active-matrix OLED [AMOLED] displays
• CPC Class Codes: H10K 59/1213 the pixel elements being TFTs
• CPC Class Codes: H10K 59/1216 the pixel elements being capacitors
• CPC Class Codes: H10K 59/131 Interconnections, e.g. wiring lines or terminals
• CPC Class Codes: H10K 59/38 comprising colour filters or colour changing media [CCM]

Abstract

An EL display having high operating performance and reliability is provided. LDD regions 15a through 15d of a switching TFT 201 formed in a pixel are formed such that they do not overlap gate electrodes 19a and 19b to provide a structure which is primarily intended for the reduction of an off-current. An LDD region 22 of a current control TFT 202 is formed such that it partially overlaps a gate electrode 35 to provide a structure which is primarily intended for the prevention of hot carrier injection and the reduction of an off-current. Appropriate TFT structures are thus provided depending on required functions to improve operational performance and reliability.

Claims

1. A semiconductor device comprising an EL element, a first transistor, a second transistor, a capacitor, a first wiring, a second wiring and a third wiring,

wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,

wherein a gate electrode of the first transistor is electrically connected to the second wiring,

wherein one of a source and a drain of the second transistor is electrically connected to the EL element,

wherein the other of the source and the drain of the second transistor is electrically connected to the third wiring,

wherein the first transistor comprises a first semiconductor region, a first insulating film over the first semiconductor region, and the gate electrode over the first insulating film,

wherein the first semiconductor region is included in the same semiconductor layer as a second semiconductor region,

wherein the second semiconductor region overlaps with a conductive film with the first insulating film provided therebetween,

wherein the third wiring is located over the conductive film,

wherein the third wiring overlaps with the conductive film with a second insulating film provided therebetween,

wherein the conductive film is configured to serve as one terminal of the capacitor,

wherein the conductive film is directly connected to the third wiring, and

wherein a region where the conductive film is directly connected to the third wiring overlaps with the second semiconductor region.

2. The semiconductor device according to claim 1, wherein the second semiconductor region is a capacitor forming semiconductor region.

3. The semiconductor device according to claim 1, wherein the gate electrode of the first transistor is double gate structure.

4. The semiconductor device according to claim 1, wherein the first transistor comprises an LDD region which does not overlap with the gate electrode of the first transistor.

5. The semiconductor device according to claim 1, wherein the second transistor comprises an LDD region which overlaps with a gate electrode of the second transistor.

6. A semiconductor device comprising an EL element, a first transistor, a second transistor, a capacitor, a first wiring, a second wiring and a third wiring,

wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,

wherein a gate electrode of the first transistor is electrically connected to the second wiring,

wherein one of a source and a drain of the second transistor is electrically connected to the EL element,

wherein the other of the source and the drain of the second transistor is electrically connected to the third wiring,

wherein the first transistor comprises a first semiconductor region, a first insulating film over the first semiconductor region, and the gate electrode over the first insulating film,

wherein the first semiconductor region is included in the same semiconductor layer as a second semiconductor region,

wherein the second semiconductor region overlaps with a conductive film with the first insulating film provided therebetween,

wherein the third wiring is located over the conductive film,

wherein the third wiring overlaps with the conductive film with a second insulating film provided therebetween,

wherein the conductive film is configured to serve as one terminal of the capacitor,

wherein the conductive film is directly connected to the third wiring,

wherein a region where the conductive film is directly connected to the third wiring overlaps with the second semiconductor region, and

wherein the conductive film is extended so as to be in parallel to the second wiring.

7. The semiconductor device according to claim 6, wherein the second semiconductor region is a capacitor forming semiconductor region.

8. The semiconductor device according to claim 6, wherein the gate electrode of the first transistor is double gate structure.

9. The semiconductor device according to claim 6, wherein the first transistor comprises an LDD region which does not overlap with the gate electrode of the first transistor.

10. The semiconductor device according to claim 6, wherein the second transistor comprises an LDD region which overlaps with a gate electrode of the second transistor.

11. A semiconductor device comprising:

a plastic substrate;

a pixel over the plastic substrate, the pixel comprising an EL element, a first transistor, a second transistor, a capacitor, a first wiring, a second wiring and a third wiring; and

a cover material comprising a plastic material, the cover material facing the plastic substrate with the pixel provided therebetween,

wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,

wherein a gate electrode of the first transistor is electrically connected to the second wiring,

wherein one of a source and a drain of the second transistor is electrically connected to the EL element,

wherein the other of the source and the drain of the second transistor is electrically connected to the third wiring,

wherein the first transistor comprises a first semiconductor region, a first insulating film over the first semiconductor region, and the gate electrode over the first insulating film,

wherein the first semiconductor region is included in the same semiconductor layer as a second semiconductor region,

wherein the second semiconductor region overlaps with a conductive film with the first insulating film provided therebetween,

wherein the third wiring is located over the conductive film,

wherein the third wiring overlaps with the conductive film with a second insulating film provided therebetween,

wherein the conductive film is configured to serve as one terminal of the capacitor,

wherein the conductive film is directly connected to the third wiring, and

wherein a region where the conductive film is directly connected to the third wiring overlaps with the second semiconductor region.

12. The semiconductor device according to claim 11, wherein the second semiconductor region is a capacitor forming semiconductor region.

13. The semiconductor device according to claim 11, wherein the gate electrode of the first transistor is double gate structure.

14. The semiconductor device according to claim 11, wherein the first transistor comprises an LDD region which does not overlap with the gate electrode of the first transistor.

15. The semiconductor device according to claim 11, wherein the second transistor comprises an LDD region which overlaps with a gate electrode of the second transistor.

16. A semiconductor device comprising:

a plastic substrate;

a pixel over the plastic substrate, the pixel comprising an EL element, a first transistor, a second transistor, a capacitor, a first wiring, a second wiring and a third wiring; and

a cover material comprising a plastic material, the cover material facing the plastic substrate with the pixel provided therebetween,

wherein one of a source and a drain of the first transistor is electrically connected to the first wiring,

wherein a gate electrode of the first transistor is electrically connected to the second wiring,

wherein one of a source and a drain of the second transistor is electrically connected to the EL element,

wherein the other of the source and the drain of the second transistor is electrically connected to the third wiring,

wherein the first transistor comprises a first semiconductor region, a first insulating film over the first semiconductor region, and the gate electrode over the first insulating film,

wherein the first semiconductor region is included in the same semiconductor layer as a second semiconductor region,

wherein the second semiconductor region overlaps with a conductive film with the first insulating film provided therebetween,

wherein the third wiring is located over the conductive film,

wherein the third wiring overlaps with the conductive film with a second insulating film provided therebetween,

wherein the conductive film is configured to serve as one terminal of the capacitor,

wherein the conductive film is directly connected to the third wiring,

wherein a region where the conductive film is directly connected to the third wiring overlaps with the second semiconductor region, and

wherein the conductive film is extended so as to be in parallel to the second wiring.

17. The semiconductor device according to claim 16, wherein the second semiconductor region is a capacitor forming semiconductor region.

18. The semiconductor device according to claim 16, wherein the gate electrode of the first transistor is double gate structure.

19. The semiconductor device according to claim 16, wherein the first transistor comprises an LDD region which does not overlap with the gate electrode of the first transistor.

20. The semiconductor device according to claim 16, wherein the second transistor comprises an LDD region which overlaps with a gate electrode of the second transistor.