Concentric capacitor structure

• US 9,293,521 B2
• Filed: 08/08/2014
• Issued: 03/22/2016
• Est. Priority Date: 03/02/2012
• Status: Active Grant

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Lin, Chi-Hsien, Liao, Hsien-Yuan, Chen, Ho-Hsiang, Yeh, Tzu-Jin, Lu, Ying-Ta
• Primary Examiner(s): Shamsuzzaman, Mohammed
• Application Number:
  US14/454,760
• Publication Number:
  US 20140374881A1
• Time in Patent Office: 592 Days
• Field of Search: 257/532, 257/309, 257/306, 257/415, 257/312, 257/418, 257/296, 324/750.3, 333/17.3, 361/303, 361/305, 361/328, 261/13, 438/689, 438/52, 438/253, 438/240, 735/143.2, 737/80, 733/143.2
• US Class Current: 1/1
• CPC Class Codes: H01L 23/5223 Capacitor integral with wiring layers
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 28/60 Electrodes
• CPC Class Codes: H01L 28/88 made by patterning layers, e.g. by etching conductive layers
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A concentric capacitor structure generally comprising concentric capacitors is disclosed. Each concentric capacitor comprises a first plurality of perimeter plates formed on a first layer of a substrate and a second plurality of perimeter plates formed on a second layer of the substrate. The first plurality of perimeter plates extend in a first direction and the second plurality of perimeter plates extend in a second direction different than the first direction. A first set of the first plurality of perimeter plates is electrically coupled to a first set of the second plurality of perimeter plates and a second set of the first plurality of perimeter plates is electrically coupled to a second set of the second plurality of perimeter plates. A plurality of capacitive cross-plates are formed in the first layer such that each cross-plate overlaps least two of the second plurality of perimeter plates.

Claims

1. A differential capacitive structure, comprising:

a semiconductor substrate comprising a first routing layer and a second routing layer;

a first concentric capacitor bank formed on the semiconductor substrate, the concentric capacitor bank comprising;

at least one concentric capacitor formed on the semiconductor substrate, wherein each of the at least one concentric capacitors comprises;

a first plurality of capacitive perimeter plates formed in the first routing layer, the first plurality of capacitive perimeter plates extending in a first direction;

a second plurality of capacitive perimeter plates formed in the second routing layer, the second plurality of capacitive perimeter plates extending in a second direction,

wherein the second direction is different than the first direction, wherein a first set of the first plurality of capacitive perimeter plates is electrically coupled to a first set of the second plurality of capacitive perimeter plates to define an outer concentric capacitive plate, and wherein a second set of the first plurality of capacitive perimeter plates is electrically coupled to a second set of the second plurality of capacitive perimeter plates to define an inner concentric capacitive plate; and

a first plurality of capacitive cross-plates formed in the first routing layer, the first plurality of capacitive cross-plates extending longitudinally in the first direction, wherein each of the first plurality of capacitive cross-plates at least partially overlaps the second plurality of capacitive perimeter plates formed in the second routing layer, and wherein each of the first plurality of capacitive cross-plates are electrically coupled to at least one of the second plurality of capacitive perimeter plates by a first set of a plurality of inter-layer vias, thereby increasing a capacitance of at least one of the outer and inner concentric capacitive plates;

a second plurality of capacitive cross-plates formed in the second routing layer, the second plurality of capacitive cross-plates extending longitudinally in the second direction, wherein each of the second plurality of capacitive cross-plates at least partially overlaps the first plurality of capacitive perimeter plates formed in the first routing layer, and wherein each of the second plurality of capacitive cross-plates are electrically coupled to at least one of the first plurality of capacitive perimeter plates by a second set of a plurality of inter-layer vias, thereby increasing the capacitance of at least one of the outer and inner concentric plates;

a switching mechanism configured to selectively couple one or more of the at least one concentric capacitors of the first concentric capacitor bank to a signal source,

wherein a third set of a plurality of inter-layer vias coupling the ends of each of the first plurality of capacitor perimeter plates to define a first continuous capacitive plate, a fourth set of a plurality of inter-layer vias coupling the ends of each of the second plurality of capacitor perimeter plates to define a second continuous capacitive plate.

2. The structure of claim 1, wherein the first direction and the second direction are orthogonal.

3. The structure of claim 1, wherein one of the outer or inner concentric capacitive plates comprises a negative capacitive plate and one of the outer or inner concentric capacitive plates comprises a positive capacitive plate.

4. The differential capacitive structure of claim 1, wherein the outer concentric capacitive plates are electrically coupled to the switch.

5. The differential capacitive structure of claim 1, wherein the switching mechanism is selected from the group consisting of metal-oxide-semiconductor field effect transistor (MOSFET), a diode, a bipolar junction transistor (BJT), a PN transistor, an NP transistor, an NPN transistor, a PNP transistor, or combinations thereof.

6. A structure comprising:

a semiconductor substrate comprising a first routing layer and a second routing layer;

at least two concentric capacitors formed on the semiconductor substrate, wherein each of the concentric capacitors comprises;

a first plurality of capacitive perimeter plates formed in the first routing layer, the first plurality of capacitive perimeter plates extending in a first direction;

a second plurality of capacitive perimeter plates formed in the second routing layer, the second plurality of capacitive perimeter plates extending in a second direction orthogonal to the first direction,

wherein a first set of the first plurality of capacitive perimeter plates is electrically coupled to a first set of the second plurality of capacitive perimeter plates to define an outer concentric capacitive plate, and wherein a second set of the first plurality of capacitive perimeter plates is electrically coupled to a second set of the second plurality of capacitive perimeter plates to define an inner concentric capacitive plate;

a first plurality of capacitive cross-plates formed in the first routing layer, the first plurality of capacitive cross-plates extending longitudinally in the first direction, wherein each of the first plurality of capacitive cross-plates at least partially overlaps the second plurality of capacitive perimeter plates formed in the second routing layer, and wherein each of the first plurality of capacitive cross-plates are electrically coupled to at least one of the second plurality of capacitive perimeter plates by a first set of a plurality of inter-layer vias, thereby increasing a capacitance of the at least one concentric capacitor;

a second plurality of capacitive cross-plates formed in the second routing layer, the second plurality of capacitive cross-plates extending longitudinally in the second direction, wherein each of the second plurality of capacitive cross-plates at least partially overlaps the first plurality of capacitive perimeter plates formed in the first routing layer, and wherein each of the second plurality of capacitive cross-plates are electrically coupled to at least one of the first plurality of capacitive perimeter plates by a second set of a plurality of inter-layer vias, thereby increasing the capacitance of the at least one concentric capacitor,

wherein a third set of a plurality of inter-layer vias coupling the ends of each of the first plurality of capacitor perimeter plates to define a first continuous capacitive plate, a fourth set of a plurality of inter-layer vias coupling the ends of each of the second plurality of capacitor perimeter plates to define a second continuous capacitive plate.

7. The structure of claim 6, comprising a switching mechanism configured to selectively couple one or more of the at least one concentric capacitors to a signal source.