Trench-based power semiconductor devices with increased breakdown voltage characteristics

• US 9,293,526 B2
• Filed: 11/02/2012
• Issued: 03/22/2016
• Est. Priority Date: 12/08/2008
• Status: Active Grant

• Current Assignee: Semiconductor Components Industries LLC (ON Semiconductor Corporation)
• Original Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Inventors: Yedinak, Joseph A., Challa, Ashok, Probst, Dean
• Primary Examiner(s): Li, Meiya
• Application Number:
  US13/667,319
• Publication Number:
  US 20140048869A1
• Time in Patent Office: 1,236 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 29/0619 with a supplementary region doped oppositely to or in rectifying contact with the semiconductor containing or contacting region, e.g. guard rings with PN or Schottky junction
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0638 for preventing surface leakage due to surface inversion layer, e.g. with channel stopper channel stoppers in combination with isolation region for integrated circuits H01L21/762
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/407 Recessed field plates, e.g. trench field plates, buried field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42368 the thickness being non-uniform
• CPC Class Codes: H01L 29/42372 characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out H01L29/42324 takes precedence
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7827 Vertical transistors H01L29/7802, H01L29/78642 take precedence
• CPC Class Codes: H01L 29/872 Schottky diodes
• CPC Class Codes: H01L 29/8725 of the trench MOS barrier type [TMBS]

Abstract

Exemplary power semiconductor devices with features providing increased breakdown voltage and other benefits are disclosed.

Claims

1. A semiconductor device comprising:

a gate runner disposed above a semiconductor region;

a trench disposed in the semiconductor region and having a first portion disposed on a first side of the gate runner and a second portion disposed on a second side of the gate runner;

a shield dielectric disposed in the semiconductor region and lining a sidewall of the trench;

a shield electrode disposed in the semiconductor region and having a first portion disposed in the first portion of the trench, the shield electrode having a second portion disposed in the second portion of the trench;

a gate dielectric disposed in the semiconductor region and lining an upper sidewall of the second portion of the trench;

a gate electrode disposed in the semiconductor region and disposed in the second portion of the trench and insulated from the second portion of the shield electrode; and

a shield runner made of a metal and disposed above the semiconductor region and having a portion contacting a top surface of the first portion of the shield electrode, the top surface of the first portion of the shield electrode being at or below a top surface of the semiconductor region.

2. The semiconductor device of claim 1, wherein the trench is a first trench functioning as an active trench,

the semiconductor device further comprising:

a second trench disposed in the semiconductor region;

a gate pad disposed above the semiconductor region;

a source pad disposed above the semiconductor region; and

a well region disposed in the semiconductor region adjacent the second trench,

the shield electrode included in the second trench being an electrically floating electrode or being coupled to a source pad,

the well region being disposed below at least one of the gate pad or the gate runner.

3. The semiconductor device of claim 2, wherein the well region is included in a first mesa in the semiconductor region,

the semiconductor device further comprising:

a second mesa disposed in the semiconductor region and adjacent the second trench, the second mesa having a width less than or equal to 1.25 times a width of the first mesa.

4. The semiconductor device of claim 1, wherein the trench is a first trench,

the semiconductor device further comprising:

a gate pad disposed above the semiconductor region;

a source pad disposed above the semiconductor region;

a second trench disposed in the semiconductor region and excluding a gate electrode;

a first mesa disposed in the semiconductor region and adjacent the first trench, the first mesa being an electrically floating mesa or being electrically coupled to the source pad; and

a second mesa region disposed in the semiconductor region and adjacent the second trench, the second mesa being an electrically floating mesa or being electrically coupled to the source pad, the second mesa being disposed below at least one of the gate pad or the gate runner.

5. The semiconductor device of claim 1, further comprising:

a contact opening disposed over the first portion of the trench, the shield runner making electrical contact to the first portion of the shield electrode through the contact opening.

6. The semiconductor device of claim 1, wherein a top surface of the second portion of the shield electrode is at a depth lower than the top surface of the first portion of the shield electrode.

7. The semiconductor device of claim 1, further comprising:

a dielectric disposed on the top surface of the semiconductor region.

8. The semiconductor device of claim 1, wherein the trench is a first trench,

the semiconductor further comprising:

a second trench disposed in the semiconductor region and including a shield electrode and excluding a gate electrode.

9. The semiconductor device of claim 1, wherein the trench is a first trench,

the semiconductor further comprising:

a second trench disposed in the semiconductor region and including a shield electrode and excluding a gate electrode, the second trench having a first portion aligned parallel to the first trench and a second portion align orthogonal to the first trench.

10. The semiconductor device of claim 1, wherein the top surface of the first portion of the shield electrode is a top surface of a shield riser portion of the first portion of the shield electrode, the shield runner is in contact with the top surface of the shield riser portion.

11. The semiconductor device of claim 1, wherein

the gate electrode is electrically coupled to the gate runner via a gate riser having at least a portion disposed above the top surface of the semiconductor region.

12. The semiconductor device of claim 1, wherein the shield runner contacts the top surface of the first portion of the shield electrode using a via.

13. The semiconductor device of claim 1, wherein the portion of the shield runner is a first portion,

the semiconductor device further comprising:

a pair of additional trenches disposed in the semiconductor region and having a mesa disposed therebetween, the mesa being doped as a p-type region, the shield runner having a second portion contacting a conductive electrode disposed in each trench from the pair of additional trenches and the mesa.

14. The semiconductor device of claim 13, wherein the first portion of the shield runner is disposed over a dielectric layer, the second portion of the shield electrode contacts the conductive electrode disposed in each trench from the pair of additional trenches and the mesa without being disposed over the dielectric layer.

15. A semiconductor device, comprising:

a first trench disposed in a semiconductor region, the first trench including a shield electrode insulated from a gate electrode;

a source pad disposed above the semiconductor region and electrically coupled to the shield electrode of the first trench;

a gate pad disposed above the semiconductor region;

a gate runner disposed above the semiconductor region and electrically coupled to the gate pad and to the gate electrode of the first trench, the first trench having a first portion disposed on a first side of the gate runner and a second portion disposed on a second side of the gate runner;

a second trench disposed in the semiconductor region, the second trench including a conductive electrode disposed therein; and

a shield runner made of a metal and disposed above the semiconductor region and contacting a top surface of a first portion of the conductive electrode included in the second trench, the top surface of the first portion of the conductive electrode included in the second trench being at or below a top surface of the semiconductor region.

16. The semiconductor device of claim 15, wherein the second trench is disposed in an edge region of the semiconductor region, the edge region being disposed outside of an active region of the semiconductor region.

17. The semiconductor device of claim 15, wherein the second trench is disposed under at least one of the gate pad and the gate runner,

the semiconductor device further comprising:

a first mesa disposed in the semiconductor region and adjacent the first trench;

a second mesa disposed in the semiconductor region and adjacent the second trench; and

a well region of a first conductivity type disposed in the semiconductor region, the well region being disposed in the second mesa.

18. The semiconductor device of claim 15, further comprising:

a well region disposed in the semiconductor region adjacent the first trench,

the conductive electrode included in the second trench being electrically floating or being coupled to the source pad,

the well region being disposed below at least one of the gate pad and the gate runner.

19. The semiconductor device of claim 18, wherein the well region is included in a first mesa,

the semiconductor device further comprising:

a second mesa adjacent the second trench, the second mesa having a width less than or equal to 1.25 times a width of the first mesa.

20. The semiconductor device of claim 15, further comprising:

a well region disposed in the semiconductor region adjacent the second trench, the well region being an electrically floating well region or being coupled to the source pad,

the well region being disposed below at least one of the gate pad or the gate runner.

21. The semiconductor device of claim 15, further comprising:

a first well region disposed in the semiconductor region adjacent the first trench, the first well region being a first electrically floating well region or being coupled to the source pad,

the first well region being disposed below at least one of the gate pad or the gate runner; and

a second well region disposed in the semiconductor region adjacent the second trench, the second well region being a second electrically floating well region or being coupled to the source pad,

the second well region being disposed below at least one of the gate pad or the gate runner.

22. The semiconductor device of claim 15, wherein the conductive electrode included in the second trench is coupled to the source pad,

the semiconductor device further comprising:

a first mesa adjacent the first trench, the first trench being disposed below at least one of the gate pad or the gate runner; and

a second mesa adjacent the second trench, the second mesa having a width less than or equal to 1.25 times a width of the first mesa.

23. The semiconductor device of claim 15, wherein the conductive electrode is a first conductive electrode included in the second trench is electrically floating,

the semiconductor device further comprising:

a well region disposed in the semiconductor region adjacent the first trench; and

a third trench including a second conductive electrode coupled to the source pad,

the well region being disposed below at least one of the gate pad or the gate runner.

24. The semiconductor device of claim 23, wherein the well region is included in a first mesa,

the semiconductor device further comprising:

a second mesa disposed between the second trench and the third trench, the second mesa having a width less than or equal to 1.25 times a width of the first mesa.

25. The semiconductor device of claim 15, wherein the conductive electrode is a first conductive electrode included in the second trench is electrically floating, the second trench is an end trench, the first trench is an active trench,

the semiconductor device further comprising:

a third trench including a second conductive electrode coupled to the source pad, the third trench being disposed between the second trench and the first trench.

26. The semiconductor device of claim 25, further comprising:

a mesa disposed between the second trench and the third trench, the mesa being an electrically floating mesa.

27. The semiconductor device of claim 25, wherein the shield runner contacts the top surface of the first portion of the shield electrode using a via.