Semiconductor switching devices with different local transconductance

• US 9,293,533 B2
• Filed: 06/20/2014
• Issued: 03/22/2016
• Est. Priority Date: 06/20/2014
• Status: Expired due to Fees

• Current Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Original Assignee: Infineon Technologies Austria Ag (Infineon Technologies AG)
• Inventors: Fachmann, Christian, Vecino Vazquez, Enrique, Willmeroth, Armin
• Primary Examiner(s): Wilson, Allan R
• Application Number:
  US14/310,055
• Publication Number:
  US 20150372087A1
• Time in Patent Office: 641 Days
• Field of Search: 257/203
• US Class Current: 1/1
• CPC Class Codes: H01L 2224/0603 Bonding areas having different sizes, e.g. different heights or widths
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique
• CPC Class Codes: H01L 27/07 the components having an active region in common
• CPC Class Codes: H01L 27/0705 comprising components of the field effect type
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/0634 Multiple reduced surface field (multi-RESURF) structures, e.g. double RESURF, charge compensation, cool, superjunction (SJ), 3D-RESURF, composite buffer (CB) structures
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/0882 Disposition
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/402 Field plates
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4232 with insulated gate
• CPC Class Codes: H01L 29/4238 characterised by the surface lay-out
• CPC Class Codes: H01L 29/49 Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET H01L29/435 takes precedence
• CPC Class Codes: H01L 29/66333 Vertical insulated gate bipolar transistors
• CPC Class Codes: H01L 29/6634 with a recess formed by etching in the source/emitter contact region H01L29/66348 takes precedence; etching of semiconductor bodies H01L21/302
• CPC Class Codes: H01L 29/66666 Vertical transistors H01L29/66712, H01L29/66742 take precedence
• CPC Class Codes: H01L 29/66712 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7395 Vertical transistors, e.g. vertical IGBT
• CPC Class Codes: H01L 29/7396 with a non planar surface, e.g. with a non planar gate or with a trench or recess or pillar in the surface of the emitter, base or collector region for improving current density or short circuiting the emitter and base regions H01L29/7398 takes precedence
• CPC Class Codes: H01L 29/7803 : structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7811 : with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7827 : Vertical transistors H01L29/7802, H01L29/78642 take precedence

Abstract

A semiconductor device includes a semiconductor substrate having an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells defining the active area and the outer rim. Each of the switchable cells includes a body region, a gate electrode structure and a source region. The active area defined by the switchable cells includes at least a first switchable region having a first transconductance and a second switchable region having a second transconductance which is different from the first transconductance.

Claims

1. A semiconductor device, comprising:

a semiconductor substrate comprising an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells defining the active area and the outer rim, wherein each of the switchable cells comprises a body region, a gate electrode structure and a source region;

a source metallization in ohmic contact with the source regions of the switchable cells; and

a gate metallization in ohmic contact with the gate electrode structures of the switchable cells,

wherein the active area defined by the switchable cells comprises at least a first switchable region having a first transconductance and at least a second switchable region having a second transconductance which is different from the first transconductance

wherein the second switchable region is arranged between the gate metallization and the first switchable region, wherein the second transconductance of the second switchable region is lower than the first transconductance of the first switchable region, and

wherein a ratio of the area of the second switchable region to the total area of the switchable regions is in a range from 5% to 50%.

2. The semiconductor device of claim 1, wherein the transconductance changes step-wise from a sub-area of the active area close to the gate metallization to a center of the active area further away from the gate metallization.

3. The semiconductor device of claim 1, wherein the plurality of switchable cells comprises at least one transistor selected from the group consisting of a MOSFET, a MISFET, an IGBT, a SJFET, and any combinations thereof.

4. The semiconductor device of claim 1, wherein each switchable cell has a given transconductance, wherein a first group of switchable cells defines the first switchable region and a second group of switchable cells different to the first group of switchable cells defines the second switchable region.

5. The semiconductor device of claim 1, wherein the gate electrode structure comprises a highly-doped polycrystalline semiconductor material and the gate metallization comprises a metal layer or a metal layer stack.

6. The semiconductor device of claim 1,

wherein the active area defined by the switchable cells comprises at least the first switchable region, at least the second switchable region, and at least a third switchable region having a third transconductance which is different from each of the first transconductance and the second transconductance,

wherein the third switchable region is arranged between the gate metallization and the second switchable region,

wherein the third transconductance of the third switchable region is lower than the second transconductance of the second switchable region, and

wherein a ratio of the total area of the second and third switchable region to the total area of the first, second and third switchable region is in a range from 5% to 50%.

7. A semiconductor device, comprising:

a semiconductor substrate comprising an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells defining the active area and the outer rim, wherein each of the switchable cells comprises a body region, a gate electrode structure and a source region;

a source metallization in ohmic contact with the source regions of the switchable cells; and

a gate metallization in ohmic contact with the gate electrode structures of the switchable cells,

wherein the active area defined by the switchable cells comprises at least a first switchable region having a first transconductance and at least a second switchable region having a second transconductance which is different from the first transconductance,

wherein the second switchable region is arranged between the gate metallization and the first switchable region, wherein the second transconductance of the second switchable region is higher than the first transconductance of the first switchable region, and

wherein a ratio of the area of the second switchable region to the total area of the switchable regions is in a range from 5% to 50%.

8. The semiconductor device of claim 7,

wherein the active area defined by the switchable cells comprises at least the first switchable region, at least the second switchable region, and at least a third switchable region having a third transconductance which is different from each of the first transconductance and the second transconductance,

wherein the third switchable region is arranged between the gate metallization and the second switchable region, wherein the third transconductance of the third switchable region is higher than the second transconductance of the second switchable region, and

wherein a ratio of the total area of the second and third switchable region to the total area of the first, second and third switchable region is in a range from 5% to 50%.

9. The semiconductor device of claim 7, wherein the transconductance changes step-wise from a sub-area of the active area close to the gate metallization to a center of the active area further away from the gate metallization.

10. The semiconductor device of claim 7, wherein the plurality of switchable cells comprises at least one transistor selected from the group consisting of a MOSFET, a MISFET, an IGBT, a SJFET, and any combinations thereof.

11. The semiconductor device of claim 7, wherein each switchable cell has a given transconductance, wherein a first group of switchable cells defines the first switchable region and a second group of switchable cells different to the first group of switchable cells defines the second switchable region.

12. The semiconductor device of claim 7, wherein the gate electrode structure comprises a highly-doped polycrystalline semiconductor material and the gate metallization comprises a metal layer or a metal layer stack.

13. A semiconductor device, comprising:

a semiconductor substrate comprising an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells defining the active area and the outer rim, wherein each of the switchable cells comprises a body region, a gate electrode structure and a source region;

a source metallization in ohmic contact with the source regions of the switchable cells; and

a gate metallization in ohmic contact with the gate electrode structures of the switchable cells,

wherein the active area defined by the switchable cells comprises at least a first switchable region having respective channel regions each with a first channel width and at least a second switchable region having respective channel regions each with a second channel width which is different to the first channel width,

wherein the second switchable region is arranged between the gate metallization and the first switchable region, wherein the second channel width of the channel regions of the second switchable region is smaller than the first channel width of the channel regions of the first switchable region, and

wherein a ratio of the area of the second switchable region to the total area of the switchable regions is in a range from 5% to 50%.

14. The semiconductor device of claim 13, wherein each switchable cell has a given channel width, wherein a first group of switchable cells defines the first switchable region and a second group of switchable cells different to the first group of switchable cells defines the second switchable region.

15. The semiconductor device of claim 13, wherein the channel width of the channel regions changes step-wise from a sub-area of the active area close to the gate metallization to a center of the active area further away from the gate metallization.

16. The semiconductor device of claim 13, wherein the active area defined by the switchable cells further comprises at least a third switchable region having respective channel regions with a third channel width which is different to the first channel width and the second channel width.

17. The semiconductor device of claim 13, wherein the second switchable region forms an outer ring region of the active area and the first switchable region forms a central region of the active area, wherein the outer ring region provides a boundary between the central region of the active area and the edge termination region.

18. The semiconductor device of claim 17, wherein the second switchable cells of the outer ring region have a channel width which is smaller than the channel width of the switchable cells of the central region.

19. The semiconductor device of claim 17, wherein the second switchable cells of the outer ring region have a channel width which is larger than the channel width of the switchable cells of the central region.

20. The semiconductor device of claim 13,

wherein the active area defined by the switchable cells comprises at least the first switchable region, at least the second switchable region, and at least a third switchable region having respective channel regions each with a third channel width which is different to each of the first channel width and second channel width,

wherein the third switchable region is arranged between the gate metallization and the second switchable region,

wherein the third channel width of the channel regions of the third switchable region is smaller than the second channel width of the channel regions of the second switchable region, and

wherein a ratio of the total area of the second and third switchable region to the total area of the first, second and third switchable region is in a range from 5% to 50%.

21. A semiconductor device, comprising:

a semiconductor substrate comprising an outer rim, a plurality of switchable cells defining an active area, and an edge termination region arranged between the switchable cells defining the active area and the outer rim, wherein each of the switchable cells comprises a body region, a gate electrode structure and a source region;

a source metallization in ohmic contact with the source regions of the switchable cells; and

a gate metallization in ohmic contact with the gate electrode structures of the switchable cells,

wherein the active area defined by the switchable cells comprises at least a first switchable region having respective channel regions each with a first channel width and at least a second switchable region having respective channel regions each with a second channel width which is different to the first channel width,

wherein the second switchable region is arranged between the gate metallization and the first switchable region, wherein the second channel width of the channel regions of the second switchable region is larger than the first channel width of the channel regions of the first switchable region, and

wherein a ratio of the area of the second switchable region to the total area of the switchable regions is in a range from 5% to 50%.

22. The semiconductor device of claim 21,

wherein the active area defined by the switchable cells comprises at least the first switchable region, at least the second switchable region, and at least a third switchable region having respective channel regions each with a third channel width which is different to each of the first channel width and second channel width,

wherein the third switchable region is arranged between the gate metallization and the second switchable region,

wherein the third channel width of the channel regions of the third switchable region is larger than the second channel width of the channel regions of the second switchable region, and

wherein a ratio of the total area of the second and third switchable region to the total area of the first, second and third switchable region is in a range from 5% to 50%.

23. The semiconductor device of claim 21, wherein each switchable cell has a given channel width, wherein a first group of switchable cells defines the first switchable region and a second group of switchable cells different to the first group of switchable cells defines the second switchable region.

24. The semiconductor device of claim 21, wherein the channel width of the channel regions changes step-wise from a sub-area of the active area close to the gate metallization to a center of the active area further away from the gate metallization.

25. The semiconductor device of claim 21, wherein the active area defined by the switchable cells further comprises at least a third switchable region having respective channel regions with a third channel width which is different to the first channel width and the second channel width.

26. The semiconductor device of claim 21, wherein the second switchable region forms an outer ring region of the active area and the first switchable region forms a central region of the active area, wherein the outer ring region provides a boundary between the central region of the active area and the edge termination region.