Semiconductor device

• US 9,293,545 B2
• Filed: 08/05/2014
• Issued: 03/22/2016
• Est. Priority Date: 11/07/2008
• Status: Active Grant

• Current Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Original Assignee: Semiconductor Energy Laboratory Co., Ltd.
• Inventors: Yamazaki, Shunpei, Akimoto, Kengo, Kawae, Daisuke
• Primary Examiner(s): Payen, Marvin
• Assistant Examiner(s): JOY, JEREMY J
• Application Number:
  US14/451,680
• Publication Number:
  US 20140339556A1
• Time in Patent Office: 595 Days
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02554 Oxides
• CPC Class Codes: H01L 21/02565 Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
• CPC Class Codes: H01L 21/02631 Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
• CPC Class Codes: H01L 27/1225 with semiconductor materials not belonging to the group IV of the periodic table, e.g. InGaZnO
• CPC Class Codes: H01L 27/1288 employing particular masking sequences or specially adapted masks, e.g. half-tone mask
• CPC Class Codes: H01L 29/41733 for thin film transistors with insulated gate
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/786 Thin film transistors, i.e. transistors with a channel being at least partly a thin film transistors having only the source or the drain region on an insulator layer H01L29/0653; thin film FinFETs H01L29/785
• CPC Class Codes: H01L 29/78618 characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure silicide contacts, electrodes in general H01L29/458
• CPC Class Codes: H01L 29/7869 having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
• CPC Class Codes: H01L 29/78696 characterised by the structure of the channel, e.g. multichannel, transverse or longitudinal shape, length or width, doping structure, or the overlap or alignment between the channel and the gate, the source or the drain, or the contacting structure of the channel H01L29/78612 takes precedence; transistors having a drain offset region or a lightly doped drain [LDD] H01L29/78621
• CPC Class Codes: H10K 10/46 Field-effect transistors, e.g. organic thin-film transistors [OTFT] H10K10/43 takes precedence
• CPC Class Codes: H10K 10/462 Insulated gate field-effect transistors [IGFETs]
• CPC Class Codes: H10K 10/466 Lateral bottom-gate IGFETs comprising only a single gate
• CPC Class Codes: H10K 10/84 Ohmic electrodes, e.g. source or drain electrodes

Abstract

A structure by which electric-field concentration which might occur between a source electrode and a drain electrode in a bottom-gate thin film transistor is relaxed and deterioration of the switching characteristics is suppressed, and a manufacturing method thereof. A bottom-gate thin film transistor in which an oxide semiconductor layer is provided over a source and drain electrodes is manufactured, and angle θ1 of the side surface of the source electrode which is in contact with the oxide semiconductor layer and angle θ2 of the side surface of the drain electrode which is in contact with the oxide semiconductor layer are each set to be greater than or equal to 20° and less than 90°, so that the distance from the top edge to the bottom edge in the side surface of each electrode is increased.

Claims

1. A semiconductor device comprising:

a glass substrate;

a gate electrode over the glass substrate;

a gate insulating film over the gate electrode;

a first metal film and a second metal film over the gate insulating film; and

an oxide semiconductor film in contact with the first metal film and the second metal film,

wherein a side surface of the first metal film faces a side surface of the second metal film, and

wherein each of the side surface of the first metal film and the side surface of the second metal film has a step in a lower end portion thereof.

2. The semiconductor device according to claim 1, wherein the oxide semiconductor film is positioned on the first metal film and the second metal film.

3. The semiconductor device according to claim 1, wherein the first metal film and the second metal film are in contact with the gate insulating film.

4. The semiconductor device according to claim 1, wherein the oxide semiconductor film comprises indium, gallium, and zinc.

5. The semiconductor device according to claim 1,

wherein a first angle of the step that is made between the side surface of the first metal film and an upper surface of the glass substrate is greater than or equal to 20°

and smaller than or equal to 90°

, and

wherein a second angle of the step that is made between the side surface of the second metal film and the upper surface of the glass substrate is greater than or equal to 20° and

smaller than or equal to 90°

.

6. The semiconductor device according to claim 1, comprising:

a first buffer layer between the oxide semiconductor film and the first metal film; and

a second buffer layer between the oxide semiconductor film and the second metal film,

wherein each of the first buffer layer and the second buffer layer has lower resistivity than the oxide semiconductor film.

7. The semiconductor device according to claim 1,

wherein the first metal film is a source electrode, and

wherein the second metal film is a drain electrode.

8. A display device comprising:

a pixel portion comprising;

the semiconductor device according to claim 1; and

a display element electrically connected to one of the first metal film and the second metal film.

9. The display device according to claim 8, wherein the display element is a liquid crystal element.

10. The display device according to claim 8, wherein the display element is a light-emitting element.

11. A semiconductor device comprising:

a glass substrate;

a gate electrode over the glass substrate;

a gate insulating film over the gate electrode;

a first metal film and a second metal film over the gate insulating film; and

an oxide semiconductor film in contact with the first metal film and the second metal film,

wherein a side surface of the first metal film faces a side surface of the second metal film,

wherein each of the side surface of the first metal film and the side surface of the second metal film has a step in a lower end portion thereof,

wherein each of the first metal film and the second metal film comprises a first layer and a second layer, and

wherein the first layer and the second layer comprises different material from each other.

12. The semiconductor device according to claim 11, wherein the oxide semiconductor film is positioned on the first metal film and the second metal film.

13. The semiconductor device according to claim 11, wherein the first metal film and the second metal film are in contact with the gate insulating film.

14. The semiconductor device according to claim 11, wherein the oxide semiconductor film comprises indium, gallium, and zinc.

15. The semiconductor device according to claim 11,

wherein a first angle of the step that is made between the side surface of the first metal film and an upper surface of the glass substrate is greater than or equal to 20°

and smaller than or equal to 90°

, and

wherein a second angle of the step that is made between the side surface of the second metal film and the upper surface of the glass substrate is greater than or equal to 20° and

smaller than or equal to 90°

.

16. The semiconductor device according to claim 11, comprising:

a first buffer layer between the oxide semiconductor film and the first metal film; and

a second buffer layer between the oxide semiconductor film and the second metal film,

wherein each of the first buffer layer and the second buffer layer has lower resistivity than the oxide semiconductor film.

17. The semiconductor device according to claim 11,

wherein the first metal film is a source electrode, and

wherein the second metal film is a drain electrode.

18. A display device comprising:

a pixel portion comprising;

the semiconductor device according to claim 11; and

a display element electrically connected to one of the first metal film and the second metal film.

19. The display device according to claim 18, wherein the display element is a liquid crystal element.

20. The display device according to claim 18, wherein the display element is a light-emitting element.