Semiconductor device

• US 9,293,548 B2
• Filed: 04/13/2015
• Issued: 03/22/2016
• Est. Priority Date: 09/15/2010
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ogura, Tsuneo
• Primary Examiner(s): Tornow, Mark
• Application Number:
  US14/685,053
• Publication Number:
  US 20150221736A1
• Time in Patent Office: 344 Days
• Field of Search: 257/139
• US Class Current: 1/1
• CPC Class Codes: H01L 29/0696 of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
• CPC Class Codes: H01L 29/1095 Body region, i.e. base region, of DMOS transistors or IGBTs cell layout H01L29/0696
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/42356 Disposition, e.g. buried gate electrode H01L29/42324 and H01L29/4234 take precedence
• CPC Class Codes: H01L 29/66348 with a recessed gate
• CPC Class Codes: H01L 29/7397 and a gate structure lying on a slanted or vertical surface or formed in a groove, e.g. trench gate IGBT
• CPC Class Codes: H01L 29/7805 in antiparallel, e.g. freewheel diode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7831 with multiple gate structure FinFETs or MuGFETs H01L29/7855, thin film transistors H01L29/78645

Abstract

According to one embodiment, a semiconductor device includes a first major electrode, a first semiconductor layer, a first conductivity-type base layer, a second conductivity-type base layer, a second semiconductor layer, a buried layer, a buried electrode, a gate insulating film, a gate electrode, and a second major electrode. The buried layer of the second conductivity type selectively is provided in the first conductivity-type base layer. The buried electrode is provided in a bottom portion of a trench which penetrates the second conductivity-type base layer to reach the buried layer. The buried electrode is in contact with the buried layer. The gate electrode is provided inside the gate insulating film in the trench. The second major electrode is provided on the second semiconductor layer and is electrically connected to the second semiconductor layer and the buried electrode.

Claims

1. A semiconductor device, comprising:

a first electrode;

a first conductivity-type base layer provided on the first electrode;

a second conductivity-type base layer provided on the first conductivity-type base layer;

a semiconductor layer of the first conductivity type provided on the second conductivity-type base layer;

a gate electrode extending through the semiconductor layer and the second conductivity-type base layer and terminating inwardly of the first conductivity-type base layer, and separated from the first conductivity-type base layer, the second conductivity-type base layer and the semiconductor layer by a gate insulating film, the gate electrode including a plurality of gate electrode portions;

a layer of the second conductivity type selectively provided in the first conductivity-type base layer;

a second electrode extending through the semiconductor layer and the second conductivity-type base layer and terminating inwardly of the layer, the second electrode being in contact with the layer, the second electrode including a first electrode portion and a second electrode portion provided adjacent to the first electrode portion, the plurality of gate electrode portions provided between the first electrode portion and second electrode portion; and

a third electrode provided on the semiconductor layer and being electrically connected to the semiconductor layer and the second electrode.

2. The device according to claim 1, wherein the plurality of gate electrode portions includes:

a first gate electrode portion provided between the first electrode portion and the second electrode portion; and

a second gate electrode portion provided adjacent to the first gate electrode portion, the first electrode portion provided between the first gate electrode portion and second gate electrode portion.

3. The device according to claim 1,

further comprising a second gate electrode provided on the second electrode via an insulating film, and electrically connected to the gate electrode.

4. The device according to claim 1, wherein

the third electrode is provided also on the second electrode so as to be in contact with an upper end of the second electrode.

5. The device according to claim 4, wherein the second conductivity-type base layer is in contact with a side face of the second electrode.

6. The device according to claim 1, wherein the layer is in contact with a bottom portion of the second electrode at a deeper position than the gate electrode.

7. The device according to claim 1, wherein the layer is in contact with a bottom face and a side face of the second electrode.

8. The device according to claim 1, wherein the second electrode is a semiconductor containing an impurity and having conductivity.

9. The device according to claim 1, wherein the semiconductor layer is provided in a striped planar pattern overlapped on the second conductivity-type base layer with a same width as the second conductivity-type base layer.

10. A semiconductor device, comprising:

a first electrode;

a first conductivity-type base layer provided on the first electrode;

a second conductivity-type base layer provided on the first conductivity-type base layer;

a semiconductor layer of the first conductivity type provided on the second conductivity-type base layer;

a gate electrode extending through the semiconductor layer and the second conductivity-type base layer and terminating inwardly of the first conductivity-type base layer, and separated from the first conductivity-type base layer, the second conductivity-type base layer and the semiconductor layer by a gate insulating film, the gate electrode including a first gate electrode portion, a second gate electrode portion, and a third gate electrode portion provided between the first gate electrode portion and second gate electrode portion, the third gate electrode portion provided adjacent to the second gate electrode portion;

a layer of the second conductivity type selectively provided in the first conductivity-type base layer;

a second electrode extending through the semiconductor layer and the second conductivity-type base layer and terminating inwardly of the layer, the second electrode being in contact with the layer, the second electrode provided between the first gate electrode portion and the third gate electrode portion, the second electrode provided adjacent to the first gate electrode portion and the third gate electrode portion; and

a third electrode provided on the semiconductor layer and being electrically connected to the semiconductor layer and the second electrode.