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Current mode PWM boost converter with frequency dithering

  • US 9,293,988 B2
  • Filed: 11/21/2013
  • Issued: 03/22/2016
  • Est. Priority Date: 12/11/2012
  • Status: Active Grant
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1. A current mode pulse width modulation (PWM) converter, comprising:

  • a boost circuit configured to receive an input voltage, and boost the input voltage to an output voltage, the boost circuit comprising an inductor and a switch configured to control flow of a current flowing through the inductor;

    a pseudo random clock generating unit configured to generate a clock signal, and vary a frequency of the clock signal;

    a voltage divider configured to receive the output voltage, and divide the output voltage to a division voltage;

    a reset signal generating circuit configured to generate a reset signal based on the division voltage and the current flowing through the boost inductor; and

    a driving signal generating circuit configured to receive the clock signal and the reset signal, and generate a driving signal of the switch based on the clock signal and the reset signal, the driving signal having a low-to-high transition corresponding to a low-to-high transition of the clock signal and having a high-to-low transition corresponding to a low-to-high transition of the reset signal,wherein in response to the pseudo random clock generating unit varying the frequency of the clock signal from a first frequency of the clock signal to a second frequency of the clock signal, the reset signal generating circuit controls activation time of the reset signal by varying a frequency of the reset signal in direct correlation to the pseudo random clock generating unit varying the frequency of the clock signal from the first frequency of the clock signal to the second frequency of the clock signal such that a duty ratio of the driving signal based on the first frequency of the clock signal is substantially equal to a duty ratio of the driving signal based on the second frequency of the clock signal, andwherein the activation time of the reset signal is reduced in direct correlation to the pseudo random clock generating unit varying the frequency of the dock signal from the first frequency of the clock signal to the second frequency of the clock signal if the frequency of the clock signal decreases from a high frequency to a low frequency and the activation time of the reset signal is increased in direct correlation to the pseudo random clock generating unit varying the frequency of the clock signal from the first frequency of the clock signal to the second frequency of the clock signal if the frequency of the clock signal increases from a low frequency to a high frequency.

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