Automatic enhanced self-driven synchronous rectification for power converters

• US 9,293,999 B1
• Filed: 09/09/2015
• Issued: 03/22/2016
• Est. Priority Date: 07/17/2015
• Status: Active Grant

• Current Assignee: Crane Electronics, Inc. (Crane Company)
• Original Assignee: Crane Electronics, Inc. (Crane Company)
• Inventors: Lam, Cuon, Song, Sovann, Nguyen, Khoa, Chen, Herman
• Primary Examiner(s): Han, Jessica
• Assistant Examiner(s): Singh, David A
• Application Number:
  US14/848,859
• Time in Patent Office: 195 Days
• Field of Search: 363/13, 363/15, 363/16, 363/20, 363/21.01, 363/21.04, 363/21.06
• US Class Current: 1/1
• CPC Class Codes: H02M 3/33546 with automatic control of the output voltage or current H02M3/33561 takes precedence
• CPC Class Codes: H02M 3/33569 having several active switching elements H02M3/3353 takes precedence
• CPC Class Codes: H02M 3/33576 having at least one active switching element at the secondary side of an isolation transformer
• CPC Class Codes: H02M 3/33592 having a synchronous rectifier circuit or a synchronous freewheeling circuit at the secondary side of an isolation transformer
• CPC Class Codes: Y02B 70/10 Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes

Abstract

Systems and methods for providing a self-driven synchronous rectification circuit for an active-clamp forward converter which includes automatically enhancing synchronous MOSFETs and maximizing input voltage range. The gate signals for the synchronous MOSFETs are derived from a unipolar magnetic coupling signal instead of a bipolarized magnetic coupling signal. The unipolar signal is retained for fully enhanced driving of the MOSFETs at low line voltage and the unipolar signal is automatically converted to a bipolar signal at high line amplitude due to line variance to maximize input voltage range by utilizing non-polarized characteristics of the MOSFET gate-to-source voltage (Vgs). The circuit permits efficient scaling for higher output voltages such as 12 volts DC or 15 volts DC, without requiring extra windings on the transformer of the forward converter.

Claims

1. An automatic enhanced self-driven synchronous rectification (AESDSR) control circuit for an active-clamp forward converter, the active clamp forward converter comprising a transformer having a primary winding and a secondary winding, a primary circuit electrically coupled to the primary winding, a secondary circuit electrically coupled to the secondary winding, the secondary circuit comprising first and second synchronous rectifying elements electrically connected in series with each other and electrically connected in parallel to the secondary winding, the first and second synchronous rectifying elements being electrically coupled together at a common node, the first and second synchronous rectifying elements comprising respective first and second control nodes, the AESDSR control circuit comprising:

a first passive synchronous rectifier (SR) control circuit comprising;

a first direct current (DC) voltage divider circuit electrically coupled between a first node of the secondary winding and the common node, the first DC voltage divider circuit having an output electrically connected to the first control node of the first synchronous rectifying element;

a first alternating current (AC) voltage divider circuit electrically coupled between the first node of the secondary winding and the common node, the first AC voltage divider circuit having an output electrically connected to the first control node of the first synchronous rectifying element; and

a first control node voltage limiter circuit electrically coupled between the first control node of the first synchronous rectifying element and the common node; and

a second passive SR control circuit comprising;

a second DC voltage divider circuit electrically coupled between a second node of the secondary winding and the common node, the second DC voltage divider circuit having an output electrically connected to the second control node of the second synchronous rectifying element;

a second AC voltage divider circuit electrically coupled between the second node of the secondary winding and the common node, the second AC voltage divider circuit having an output electrically connected to the second control node of the second synchronous rectifying element; and

a second control node voltage limiter circuit electrically coupled between the second control node of the second synchronous rectifying element and the common node.

2. The AESDSR control circuit of claim 1 wherein the first passive SR control circuit comprises a first peak current limiter circuit electrically coupled between the common node and the first node of the secondary winding, and the second passive SR control circuit comprises a second peak current limiter circuit electrically coupled between the common node and the second node of the secondary winding.

3. The AESDSR control circuit of claim 2 wherein the first peak current limiter circuit comprises a first resistor coupled in parallel with a first diode, and the second peak current limiter circuit comprises a second resistor coupled in parallel with a second diode.

4. The AESDSR control circuit of claim 1 wherein each of the first DC voltage divider circuit and the second DC voltage divider circuit comprises at least two resistors.

5. The AESDSR control circuit of claim 1 wherein the first AC voltage divider circuit comprises a capacitor and an internal capacitance of the first synchronous rectifying element, and the second AC voltage divider circuit comprises a capacitor and an internal capacitance of the second synchronous rectifying element.

6. The AESDSR control circuit of claim 1 wherein the first control node voltage limiter circuit comprises a first zener diode and a second zener diode electrically connected anode-to-anode with each other, and the second control node voltage limiter circuit comprises a third zener diode and a fourth zener diode electrically connected anode-to-anode with each other.

7. The AESDSR control circuit of claim 1 wherein the first control node voltage limiter circuit comprises:

a first zener diode and a second zener diode each comprising an anode and a cathode, the cathode of the first zener diode electrically coupled to the first control node, the cathode of the second zener diode electrically coupled to the common node, and the anode of the first zener diode electrically coupled to the anode of the second zener diode; and

the second control node voltage limiter circuit comprises;

a third zener diode and a fourth zener diode each comprising an anode and a cathode, the cathode of the third zener diode electrically coupled to the second control node, the cathode of the fourth zener diode electrically coupled to the common node, and the anode of the third zener diode electrically coupled to the anode of the fourth zener diode.

8. An automatic enhanced self-driven synchronous rectification (AESDSR) control circuit for an active-clamp forward converter, the active clamp forward converter comprising a transformer having a primary winding and a secondary winding, a primary circuit electrically coupled to the primary winding, a secondary circuit electrically coupled to the secondary winding, the secondary circuit comprising first and second synchronous rectifying elements electrically connected in series with each other and electrically connected in parallel to the secondary winding, the first and second synchronous rectifying elements being electrically coupled together at a common node, the first and second synchronous rectifying elements comprising respective first and second control nodes, the AESDSR circuit comprising:

a first passive synchronous rectifier (SR) control circuit comprising;

a first direct current (DC) voltage divider circuit electrically coupled between a first node of the secondary winding and the common node, the first DC voltage divider circuit having an output electrically connected to the first control node of the first synchronous rectifying element, the first DC voltage divider comprising at least two resistors;

a first alternating current (AC) voltage divider circuit electrically coupled between the first node of the secondary winding and the common node, the first AC voltage divider circuit having an output electrically connected to the first control node of the first synchronous rectifying element, the first AC voltage divider circuit comprises a capacitor and an internal capacitance of the first synchronous rectifying element; and

a first control node voltage limiter circuit electrically coupled between the first control node of the first synchronous rectifying element and the common node, the first control node voltage limiter circuit comprises a first zener diode and a second zener diode each comprising an anode and a cathode, the cathode of the first zener diode electrically coupled to the first control node, the cathode of the second zener diode electrically coupled to the common node, and the anode of the first zener diode electrically coupled to the anode of the second zener diode; and

a second passive synchronous rectifier (SR) control circuit comprising;

a second direct current (DC) voltage divider circuit electrically coupled between a second node of the secondary winding and the common node, the second DC voltage divider circuit having an output electrically connected to the second control node of the second synchronous rectifying element, the second DC voltage divider comprising at least two resistors;

a second alternating current (AC) voltage divider circuit electrically coupled between the second node of the secondary winding and the common node, the second AC voltage divider circuit having an output electrically connected to the second control node of the second synchronous rectifying element, the second AC voltage divider circuit comprises a capacitor and an internal capacitance of the second synchronous rectifying element; and

a second control node voltage limiter circuit electrically coupled between the second control node of the second synchronous rectifying element and the common node, the second control node voltage limiter circuit comprises a third zener diode and a fourth zener diode each comprising an anode and a cathode, the cathode of the third zener diode electrically coupled to the second control node, the cathode of the fourth zener diode electrically coupled to the common node, and the anode of the third zener diode electrically coupled to the anode of the fourth zener diode.

9. The AESDSR control circuit of claim 8 wherein the first passive SR control circuit comprises a first peak current limiter circuit electrically coupled between the common node and the first node of the secondary winding, and the second passive SR control circuit comprises a second peak current limiter circuit electrically coupled between the common node and the second node of the secondary winding.

10. The AESDSR control circuit of claim 9 wherein the first peak current limiter circuit comprises a first resistor coupled in parallel with a first diode, and the second peak current limiter circuit comprises a second resistor coupled in parallel with a second diode.

11. An active-clamp forward converter, comprising:

a transformer having a primary winding and a secondary winding;

a primary circuit electrically coupled to the primary winding;

a secondary circuit electrically coupled to the secondary winding, the secondary circuit comprising first and second synchronous rectifying elements electrically connected in series with each other and electrically connected in parallel to the secondary winding, the first and second synchronous rectifying elements being electrically coupled together at a common node, the first and second synchronous rectifying elements comprising respective first and second control nodes; and

an automatic enhanced self-driven synchronous rectification (AESDSR) control circuit comprising;

a first passive synchronous rectifier (SR) control circuit comprising;

a first direct current (DC) voltage divider circuit electrically coupled between a first node of the secondary winding and the common node, the first DC voltage divider circuit having an output electrically connected to the first control node of the first synchronous rectifying element;

a first alternating current (AC) voltage divider circuit electrically coupled between the first node of the secondary winding and the common node, the first AC voltage divider circuit having an output electrically connected to the first control node of the first synchronous rectifying element; and

a first control node voltage limiter circuit electrically coupled between the first control node of the first synchronous rectifying element and the common node; and

a second passive SR control circuit comprising;

a second DC voltage divider circuit electrically coupled between a second node of the secondary winding and the common node, the second DC voltage divider circuit having an output electrically connected to the second control node of the second synchronous rectifying element;

a second AC voltage divider circuit electrically coupled between the second node of the secondary winding and the common node, the second AC voltage divider circuit having an output electrically connected to the second control node of the second synchronous rectifying element; and

a second control node voltage limiter circuit electrically coupled between the second control node of the second synchronous rectifying element and the common node.

12. The active-clamp forward converter of claim 11 wherein each of the first and second synchronous rectifying elements comprises a metal oxide semiconductor field effect transistor.

13. The active-clamp forward converter of claim 11 wherein the first passive SR control circuit comprises a first peak current limiter circuit electrically coupled between the common node and the first node of the secondary winding, and the second passive SR control circuit comprises a second peak current limiter circuit electrically coupled between the common node and the second node of the secondary winding.

14. The active-clamp forward converter of claim 13 wherein the first peak current limiter circuit comprises a first resistor coupled in parallel with a first diode, and the second peak current limiter circuit comprises a second resistor coupled in parallel with a second diode.

15. The active-clamp forward converter of claim 11 wherein each of the first DC voltage divider circuit and the second DC voltage divider circuit comprises at least two resistors.

16. The active-clamp forward converter of claim 11 wherein the first AC voltage divider circuit comprises a capacitor and an internal capacitance of the first synchronous rectifying element, and the second AC voltage divider circuit comprises a capacitor and an internal capacitance of the second synchronous rectifying element.

17. The active-clamp forward converter of claim 11 wherein the first control node voltage limiter circuit comprises a first zener diode and a second zener diode electrically connected anode-to-anode with each other, and the second control node voltage limiter circuit comprises a third zener diode and a fourth zener diode electrically connected anode-to-anode with each other.

18. The active-clamp forward converter of claim 11 wherein the first control node voltage limiter circuit comprises:

a first zener diode and a second zener diode each comprising an anode and a cathode, the cathode of the first zener diode electrically coupled to the first control node, the cathode of the second zener diode electrically coupled to the common node, and the anode of the first zener diode electrically coupled to the anode of the second zener diode; and

the second control node voltage limiter circuit comprises;

a third zener diode and a fourth zener diode each comprising an anode and a cathode, the cathode of the third zener diode electrically coupled to the second control node, the cathode of the fourth zener diode electrically coupled to the common node, and the anode of the third zener diode electrically coupled to the anode of the fourth zener diode.

19. An active-clamped power converter, comprising:

a pair of input terminals supplied with input direct current (DC) voltage;

a pair of output terminals which outputs DC voltage;

a transformer having a primary winding and a secondary winding;

a primary circuit electrically coupled to the input terminals and the primary winding of the transformer;

a secondary circuit electrically coupled to the output terminals and the secondary winding of the transformer;

a control circuit operatively coupled to at least one of the output terminals to control the primary circuit to produce a main switch control signal and a subsidiary switch control signal;

the primary circuit comprising;

a main switch electrically coupled in series with the primary winding of the transformer to form a primary series connection circuit and operable responsive to the main switch control signal to be selectively put into an on-state and an off-state, the primary series connection circuit being electrically coupled between the input terminals; and

a first series circuit, connected in parallel with the primary winding of the transformer, comprising a clamping capacitor and a subsidiary switch which is operable responsive to the subsidiary control signal to be selectively put into an on-state and an off-state, the subsidiary switch carrying out reverse operation with the main switch to clamp a primary reset voltage appearing at the primary winding of the transformer;

the secondary circuit comprising;

a synchronous rectifier connected in parallel to the secondary winding of the transformer, the synchronous rectifier comprising;

a second series circuit, electrically coupled in parallel to the secondary winding of the transformer, the second series circuit comprising first and second synchronous rectifying elements which are operable in synchrony with the main switch, the first and the second synchronous rectifying elements having first and second control nodes, respectively, the first and the second synchronous rectifying elements being joined together at a common node;

a first passive synchronous rectifier (SR) control circuit comprising;

a first direct current (DC) voltage divider circuit electrically coupled between a first node of the secondary winding and the common node, the first DC voltage divider circuit having an output electrically connected to the first control node of the first synchronous rectifying element;

a first alternating current (AC) voltage divider circuit electrically coupled between the first node of the secondary winding and the common node, the first AC voltage divider circuit having an output electrically connected to the first control node of the first synchronous rectifying element; and

a first control node voltage limiter circuit electrically coupled between the first control node of the first synchronous rectifying element and the common node; and

a second passive SR control circuit comprising;

a second DC voltage divider circuit electrically coupled between a second node of the secondary winding and the common node, the second DC voltage divider circuit having an output electrically connected to the second control node of the second synchronous rectifying element;

a second AC voltage divider circuit electrically coupled between the second node of the secondary winding and the common node, the second AC voltage divider circuit having an output electrically connected to the second control node of the second synchronous rectifying element; and

a second control node voltage limiter circuit electrically coupled between the second control node of the second synchronous rectifying element and the common node.

20. The active-clamp forward converter of claim 19 wherein the first passive SR control circuit comprises a first peak current limiter circuit electrically coupled between the common node and the first node of the secondary winding, and the second passive SR control circuit comprises a second peak current limiter circuit electrically coupled between the common node and the second node of the secondary winding.

21. The active-clamp forward converter of claim 20 wherein the first peak current limiter circuit comprises a first resistor coupled in parallel with a first diode, and the second peak current limiter circuit comprises a second resistor coupled in parallel with a second diode.

22. The active-clamp forward converter of claim 19 wherein each of the first DC voltage divider circuit and the second DC voltage divider circuit comprises at least two resistors.

23. The active-clamp forward converter of claim 19 wherein the first AC voltage divider circuit comprises a capacitor and an internal capacitance of the first synchronous rectifying element, and the second AC voltage divider circuit comprises a capacitor and an internal capacitance of the second synchronous rectifying element.

24. The active-clamp forward converter of claim 19 wherein the first control node voltage limiter circuit comprises a first zener diode and a second zener diode electrically connected anode-to-anode with each other, and the second control node voltage limiter circuit comprises a third zener diode and a fourth zener diode electrically connected anode-to-anode with each other.

25. The active-clamp forward converter of claim 19 wherein the first control node voltage limiter circuit comprises:

a first zener diode and a second zener diode each comprising an anode and a cathode, the cathode of the first zener diode electrically coupled to the first control node, the cathode of the second zener diode electrically coupled to the common node, and the anode of the first zener diode electrically coupled to the anode of the second zener diode; and

the second control node voltage limiter circuit comprises;

a third zener diode and a fourth zener diode each comprising an anode and a cathode, the cathode of the third zener diode electrically coupled to the second control node, the cathode of the fourth zener diode electrically coupled to the common node, and the anode of the third zener diode electrically coupled to the anode of the fourth zener diode.