CMOS based RF antenna switch

• US 9,294,050 B2
• Filed: 09/23/2013
• Issued: 03/22/2016
• Est. Priority Date: 09/23/2012
• Status: Active Grant

• Current Assignee: DSP Group Ltd. (Synaptics Incorporated)
• Original Assignee: DSP Group Ltd. (Synaptics Incorporated)
• Inventors: Mostov, Alexander, Hasson, Yaron
• Primary Examiner(s): Hsieh, Ping
• Assistant Examiner(s): Yang, James
• Application Number:
  US14/034,081
• Publication Number:
  US 20140087672A1
• Time in Patent Office: 911 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: B82Y 10/00 Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic
• CPC Class Codes: B82Y 40/00 Manufacture or treatment of nanostructures
• CPC Class Codes: H01F 19/04 Transformers or mutual inductances suitable for handling frequencies considerably beyond the audio range resonant circuits H03H
• CPC Class Codes: H01F 27/2804 Printed windings
• CPC Class Codes: H01F 27/29 Terminals; Tapping arrangements for signal inductances
• CPC Class Codes: H01F 38/00 Adaptations of transformers or inductances for specific applications or functions
• CPC Class Codes: H01F 38/14 Inductive couplings for wireless supply or distribution of electric power using inductive coupling H02J50/10
• CPC Class Codes: H01L 2223/6611 Wire connections
• CPC Class Codes: H01L 2223/6655 Matching arrangements, e.g. arrangement of inductive and capacitive components
• CPC Class Codes: H01L 2223/6672 for integrated passive components, e.g. semiconductor device with passive components only integrated circuits with passive components only per se H01L27/01
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 23/5227 Inductive arrangements or effects of, or between, wiring layers other inductive arrangements H01L23/645
• CPC Class Codes: H01L 23/645 Inductive arrangements H01L23/647, H01L23/66 take precedence
• CPC Class Codes: H01L 23/66 High-frequency adaptations
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H02M 1/0012 Control circuits using digital or numerical techniques in DC/DC converters H02M3/157, H02M3/33515; in DC-AC converters H02M7/53873
• CPC Class Codes: H02M 3/04 by static converters
• CPC Class Codes: H02M 3/1563 : without using an external clock H02M3/158 takes precedence
• CPC Class Codes: H03F 1/02 : Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
• CPC Class Codes: H03F 1/0216 : Continuous control
• CPC Class Codes: H03F 1/0227 : using supply converters
• CPC Class Codes: H03F 1/0238 : using supply converters
• CPC Class Codes: H03F 1/0261 : with control of the polarisation voltage or current, e.g. gliding Class A
• CPC Class Codes: H03F 1/26 : Modifications of amplifiers to reduce influence of noise generated by amplifying elements
• CPC Class Codes: H03F 1/565 : using inductive elements
• CPC Class Codes: H03F 2200/102 : A non-specified detector of a signal envelope being used in an amplifying circuit
• CPC Class Codes: H03F 2200/105 : A non-specified detector of the power of a signal being used in an amplifying circuit
• CPC Class Codes: H03F 2200/18 : the bias of the gate of a FET being controlled by a control signal
• CPC Class Codes: H03F 2200/294 : the amplifier being a low noise amplifier [LNA]
• CPC Class Codes: H03F 2200/387 : A circuit being added at the output of an amplifier to adapt the output impedance of the amplifier
• CPC Class Codes: H03F 2200/432 : Two or more amplifiers of different type are coupled in parallel at the input or output, e.g. a class D and a linear amplifier, a class B and a class A amplifier
• CPC Class Codes: H03F 2200/451 : the amplifier being a radio frequency amplifier
• CPC Class Codes: H03F 2200/504 : the supply voltage or current being continuously controlled by a controlling signal, e.g. the controlling signal of a transistor implemented as variable resistor in a supply path for, an IC-block showed amplifier
• CPC Class Codes: H03F 2200/534 : Transformer coupled at the input of an amplifier
• CPC Class Codes: H03F 2200/537 : A transformer being used as coupling element between two amplifying stages
• CPC Class Codes: H03F 2200/541 : Transformer coupled at the output of an amplifier
• CPC Class Codes: H03F 2203/21106 : An input signal being distributed in parallel over the inputs of a plurality of power amplifiers
• CPC Class Codes: H03F 2203/21142 : Output signals of a plurality of power amplifiers are parallel combined to a common output
• CPC Class Codes: H03F 3/19 : with semiconductor devices only
• CPC Class Codes: H03F 3/193 : with field-effect devices H03F3/195 takes precedence
• CPC Class Codes: H03F 3/195 : in integrated circuits
• CPC Class Codes: H03F 3/21 : with semiconductor devices only H03F3/245 takes precedence
• CPC Class Codes: H03F 3/211 : using a combination of several amplifiers H03F3/60 takes precedence
• CPC Class Codes: H03F 3/213 : in integrated circuits
• CPC Class Codes: H03F 3/24 : of transmitter output stages
• CPC Class Codes: H03F 3/245 : with semiconductor devices only
• CPC Class Codes: H03F 3/265 : with field-effect transistors only
• CPC Class Codes: H03F 3/45179 : using MOSFET transistors as the active amplifying circuit H03F3/45278 takes precedence
• CPC Class Codes: H03F 3/68 : Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics power amplifiers using a combination of several semiconductor amplifiers H03F3/211; combinations of amplifiers using coupling networks with distributed constants H03F3/602
• CPC Class Codes: H04B 1/0475 : with means for limiting noise, interference or distortion H04B1/0483 takes precedence
• CPC Class Codes: H04B 1/40 : Circuits
• CPC Class Codes: H04B 1/44 : Transmit/receive switching
• CPC Class Codes: H04B 2001/045 : with means for improving efficiency
• CPC Class Codes: H04L 27/0002 : analog front ends; means for connecting modulators, demodulators or transceivers to a transmission line duplex arrangements H04L5/143
• CPC Class Codes: Y02D 30/70 : in wireless communication networks

Abstract

A novel and useful radio frequency (RF) front end module (FEM) circuit that provides high linearity and power efficiency and meets the requirements of modern wireless communication standards such as 802.11 WLAN, 3G and 4G cellular standards, Bluetooth, ZigBee, etc. The configuration of the FEM circuit permits the use of common, relatively low cost semiconductor fabrication techniques such as standard CMOS processes. The FEM circuit includes a power amplifier made up of one or more sub-amplifiers having high and low power circuits and whose outputs are combined to yield the total desired power gain. An integrated multi-tap transformer having primary and secondary windings arranged in a novel configuration provide efficient power combining and transfer to the antenna of the power generated by the individual sub-amplifiers.

Claims

1. A semiconductor antenna switch, comprising:

a first antenna port for coupling to a first antenna;

a second antenna port for coupling to a second antenna;

a transmit/receive switch port for coupling to either said first antenna or said second antenna in accordance with a respective first control signal and a second control signal;

a matching network coupled to said transmit/receive switch port;

a first transistor switch coupled in series between said first antenna port and said matching network;

a second transistor switch coupled in series between said second antenna port and said matching network;

a first impedance coupled between a bulk terminal of said first transistor switch to V_ss;

a second impedance coupled between a bulk terminal of said second transistor switch to V_ss;

a first control circuit operative to reverse bias drain and source terminals of said first transistor switch with respect to a gate terminal thereof when said first transistor switch is placed in an off state; and

a second control circuit operative to reverse bias drain and source terminals of said second transistor switch with respect to a gate terminal thereof when said second transistor switch is placed in an off state.

2. The semiconductor antenna switch according to claim 1, further comprising an inductor in series between said first antenna port and said first switch.

3. The semiconductor antenna switch according to claim 2, wherein said inductor comprises a bond wire.

4. The semiconductor antenna switch according to claim 1, further comprising an inductor in series between said second antenna port and said second switch.

5. The semiconductor antenna switch according to claim 4, wherein said inductor comprises a bond wire.

6. The semiconductor antenna switch according to claim 1, wherein said first switch is rendered conductive and said second switch is rendered nonconductive thereby coupling said first antenna port to said transmit/receive port.

7. The semiconductor antenna switch according to claim 1, wherein said first switch is rendered nonconductive and said second switch is rendered conductive thereby coupling said second antenna port to said transmit/receive port.

8. The semiconductor antenna switch according to claim 1, wherein said matching network comprises one or more inductors.

9. The semiconductor antenna switch according to claim 8, wherein said one or more inductors comprise one or more bond wires.

10. The semiconductor antenna switch according to claim 1, wherein said first switch is disabled for application with a single antenna.

11. The semiconductor antenna switch according to claim 1, further comprising:

a first dc blocking capacitor coupled in series between said first transistor switch and said first antenna port and a second dc blocking capacitor in series between said first transistor switch and said matching network; and

a third dc blocking capacitor coupled in series between said second transistor switch and said second antenna port and a fourth dc blocking capacitor in series between said second transistor switch and said matching network.

12. A semiconductor antenna switch, comprising:

a first antenna port for coupling to a first antenna;

a second antenna port for coupling to a second antenna;

a transmit/receive switch port for coupling said first antenna and said second antenna to an RX circuit and a TX circuit in accordance with a respective first control signal and a second control signal;

a first field effect transistor (FET) switch having bulk, source, drain and gate terminals, the drain terminal coupled to said first antenna port, the source terminal coupled to said transmit/receive switch port, the gate terminal operative to receive source drain and gate signals for controlling said first FET switch;

a second field effect transistor (FET) switch having bulk, source, drain and gate terminals, the drain terminal coupled to said second antenna port, the source terminal coupled to said transmit/receive switch port, the gate terminal operative to receive source, drain and gate signals for controlling said second FET switch;

a first impedance coupled between the bulk terminal of said first transistor switch to V_ss;

a second impedance coupled between the bulk terminal of said second transistor switch to V_ss;

a first control circuit operative to generate said source, drain and gate signals applied to said first FET switch, wherein the drain and source terminals of of said first FET switch are revere biased with respect to the gate terminal when the first FET switch is placed in an off state; and

a second control circuit operative to generate said source, drain and gate signals applied to said second FET switch, wherein the drain and source terminals of said second FET switch are revere biased with respect to the gate terminal when the second FET switch is placed in an off state.

13. The semiconductor antenna switch according to claim 12, further comprising an inductor in series between said first antenna port and said first FET switch.

14. The semiconductor antenna switch according to claim 13, wherein said inductor comprises a bond wire.

15. The semiconductor antenna switch according to claim 12, further comprising an inductor in series between said second antenna port and said second FET switch.

16. The semiconductor antenna switch according to claim 15, wherein said inductor comprises a bond wire.

17. The semiconductor antenna switch according to claim 12, further comprising a matching network disposed between said transmit/receive port and the source terminals of said first FET switch and said second FET switch.

18. The semiconductor antenna switch according to claim 12, wherein said first FET switch is rendered conductive and said second FET switch is rendered nonconductive thereby coupling said first antenna port to said transmit/receive port.

19. The semiconductor antenna switch according to claim 12, wherein said first FET switch is rendered nonconductive and said second FET switch is rendered conductive thereby coupling said second antenna port to said transmit/receive port.

20. The semiconductor antenna switch according to claim 12, wherein said matching network comprises one or more inductors.

21. The semiconductor antenna switch according to claim 20, wherein said one or more inductors comprise one or more bond wires.

22. The semiconductor antenna switch according to claim 12, wherein said first FET switch is disabled for application with a single antenna.

23. A method of antenna switching, the method comprising:

using a first transistor switch to couple in series a first antenna port and a transmit/receive switch port;

using a second transistor switch to couple in series a second antenna port and a transmit/receive switch port;

coupling a first impedance between a bulk terminal of said first transistor switch to V_ss;

coupling a second impedance between a bulk terminal of said second transistor switch to V_ss;

reverse biasing drain and source terminals of said first transistor switch with respect to a gate terminal thereof when said first transistor switch is placed in an off state; and

reverse biasing drain and source terminals of said second transistor switch with respect to a gate terminal thereof when said second transistor switch is placed in an off state.