Level shift circuit utilizing resistance in semiconductor substrate

• US 9,294,093 B2
• Filed: 01/27/2015
• Issued: 03/22/2016
• Est. Priority Date: 11/25/2010
• Status: Active Grant

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Akahane, Masashi
• Primary Examiner(s): LE, DINH THANH
• Application Number:
  US14/607,036
• Publication Number:
  US 20150137852A1
• Time in Patent Office: 420 Days
• Field of Search: 327/306, 327/333, 326 82- 83, 326 61- 63
• US Class Current: 1/1
• CPC Class Codes: H03K 17/04123 in field-effect transistor switches
• CPC Class Codes: H03K 17/687 the devices being field-effect transistors
• CPC Class Codes: H03K 19/017509 Interface arrangements
• CPC Class Codes: H03K 2217/0063 High side switches, i.e. the higher potential [DC] or life wire [AC] being directly connected to the switch and not via the load
• CPC Class Codes: H03K 3/356182 with additional means for controlling the main nodes

Abstract

An apparatus such as a level shift circuit includes a first signal output device configured to output a first level shifting signal, a second signal output device configured to output a second level shifting signal, and first and second detector devices. The level shifting signals are to control an output switching element of a high potential side of an output device that includes a power source and a load. The first and second detector devices are respectively configured to compare the first and second level shifting signals to a reference signal and output respective first and second comparison result signals. The first and second comparison result signals are configured to at least partly control switching of the first and second level shifting signals based at least in part on the presence of a parasitic resistance.

Claims

1. An apparatus, comprising:

a first signal output device configured to output a first level shifting signal and including a first resistance;

a second signal output device configured to output a second level shifting signal and including a second resistance;

wherein the first level shifting signal and the second level shifting signal are to control an output switching element of a high potential side of an output device comprising a power source and a load;

a first detector device configured to compare the first level shifting signal to a reference signal and output a first comparison result signal to a first switching element coupled to the first resistance; and

a second detector device configured to compare the second level shifting signal to the reference signal and output a second comparison result signal to a second switching element coupled to the second resistance;

wherein

the first comparison result signal and second comparison result signals are configured to at least partly control switching of the first switching element and the second switching element, and

each of the resistance and the second resistance is a parasitic resistance in a semiconductor substrate included in the apparatus.

2. The apparatus of claim 1, wherein at least one of the first and detector devices comprises:

a comparator having the reference signal and one of the first and second level shifting signals as an input; and

a delay device having one of the first and second level shifting signals as an input.

3. The apparatus of claim 2, wherein at least one of the first and second detector devices further comprises a logic device having an output of the comparator and an output of the delay device as inputs.