Phase-locked loop circuit with improved performance
First Claim
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1. A phase-locked loop circuit, comprising:
- a first phase detector receiving a first reference signal with a first reference frequency and a first feedback signal with a first feedback frequency to generate a first up/down signal;
a first charge pump comprising a positive output node and a negative output node, wherein the first charge pump receives the first up/down signal to generate a first current signal;
a capacitor, coupled between the negative output node of the first charge pump and the ground; and
a capacitor multiplier, coupled to the negative output node of the first charge pump, receiving the first reference signal and the first feedback signal to generate a second current signal, wherein the second current signal is the first current signal divided by a first scaling number.
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Abstract
A phase-locked loop circuit includes a phase detector, a charge pump, a capacitor, and a capacitor multiplier. The phase detector receives a reference frequency and a feedback frequency to generate a up/down signal. The charge pump, which includes a positive node and a negative node, receives the up/down signal to generate a first current. The capacitor is coupled to the negative node. The capacitor multiplier, coupled to the negative node, generates a second current which is the first current divided by a first scaling number.
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Citations
22 Claims
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1. A phase-locked loop circuit, comprising:
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a first phase detector receiving a first reference signal with a first reference frequency and a first feedback signal with a first feedback frequency to generate a first up/down signal; a first charge pump comprising a positive output node and a negative output node, wherein the first charge pump receives the first up/down signal to generate a first current signal; a capacitor, coupled between the negative output node of the first charge pump and the ground; and a capacitor multiplier, coupled to the negative output node of the first charge pump, receiving the first reference signal and the first feedback signal to generate a second current signal, wherein the second current signal is the first current signal divided by a first scaling number. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A phase-locked loop circuit, comprising:
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a first phase detector receiving a first reference signal with a first reference frequency and a first feedback signal with a first feedback frequency to generate a first up/down signal; a first charge pump comprising a first output node, wherein the first charge pump receives the first up/down signal to generate a first current signal at the first output node; a capacitor, coupled to a second output node; and a capacitor multiplier, comprising the second output node, receiving the first reference signal and the first feedback signal to generate a second current signal on the second output node, wherein the second current signal is reversed phase to the first current signal. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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Specification