TWACS transmitter and receiver

• US 9,294,147 B2
• Filed: 09/22/2014
• Issued: 03/22/2016
• Est. Priority Date: 10/01/2013
• Status: Active Grant

• Current Assignee: Aclara Technologies LLC (Hubbell, Inc.)
• Original Assignee: Aclara Technologies LLC (Hubbell, Inc.)
• Inventors: Rieken, David W., Hessling, John B. Jr.
• Primary Examiner(s): KASSA, ZEWDU A
• Application Number:
  US14/492,617
• Publication Number:
  US 20150092868A1
• Time in Patent Office: 547 Days
• Field of Search: 375/260, 375/259, 375/316, 375/295, 375/219
• US Class Current: 1/1
• CPC Class Codes: H04B 15/02 Reducing interference from electric apparatus by means located at or near the interfering apparatus
• CPC Class Codes: H04B 2203/5412 by modofying wave form of the power source
• CPC Class Codes: H04B 2203/5433 Remote metering
• CPC Class Codes: H04B 3/542 the information being in digital form

Abstract

As disclosed, a two-way automatic communications system (TWACS) and method are used by an electrical utility in which outbound messages are sent from the utility to a consumer and inbound messages are sent from the consumer to the utility. The respective outbound and inbound messages are sent and received over the utility'"'"'s power distribution system. A receiver including an analog filter component, an A/D converter and a digital processor detects the outbound messages. A substation transceiver is configured for sending analog outbound messages from the utility to a consumer. A transponder is configured for sending inbound messages to the transceiver from the consumer to the utility, the respective outbound and inbound messages being modulated on a mains signal of the utility'"'"'s power distribution system. The receiver in another form includes an analog filter component, a detecting circuit and a demodulator.

Claims

1. In a two-way automatic communications system (TWACS) used by an electrical utility in which outbound messages are sent from the utility to a consumer and inbound messages are sent from the consumer to the utility, the respective outbound and inbound messages being sent and received over the utility'"'"'s power distribution system, a receiver for detecting the outbound messages, said receiver comprising:

an analog filter component receiving the analog outbound signal including an outbound message to provide a filtered signal;

an A/D converter converting the filtered signal to a corresponding digitized signal and providing the corresponding digitized signal; and

a digital processor executing;

a digital preprocessor component receiving the corresponding digitized signal, preprocessing the received corresponding digitized signal to provide a preprocessed digital signal; and

a digital symbol determination component receiving the preprocessed digital signal and including a two-dimensional digital demodulating component for demodulating the received preprocessed digital signal to provide the outbound message wherein the symbol determination component comprises;

a digital preamble detector for receiving the preprocessed digital signal and providing a symbol synchronization signal and a weight vector w corresponding to the preprocessed digital signal; and

a digital symbol estimator component for receiving the preprocessed digital signal and for receiving the weight vector w to provide noise product signal which is;

(1) selectively sampled by the synchronization signal to provide a first dimension γ

₁ of the outbound message, and

(2) delayed by a one-half cycle multiple (z<sup>−

2</sup>) and selectively sampled by the synchronization signal to provide a second dimension γ

₂ of the outbound message, wherein the first and second dimensions γ

₁ and γ

₂ provide the outbound message.

2. The receiver of claim 1 wherein one of the following:

(a) the two-dimensional digital demodulating component comprises a digital processor demodulating the corresponding digitized signal by detecting a bit modulation at a third zero crossing of the mains signal after a bit modulation at a second zero crossing of the mains signal and by detecting a bit modulation at a third zero crossing of the mains signal before a bit modulation at the fourth zero crossing indicating a two bit binary number;

(b) a bit modulation detector circuit detects bit modulations in the filtered signal to provide a corresponding pulsed signal including the outbound message; and

wherein the two-dimensional digital demodulating component comprises a controller demodulating the corresponding pulsed signal by detecting a pulse at a third zero crossing of the mains signal after a pulse at a second zero crossing of the mains signal and by detecting a pulse at a third zero crossing of the mains signal before a pulse at the fourth zero crossing indicating a two bit binary number;

(c) the two-dimensional digital demodulating component comprises a digital processor demodulating the corresponding digitized signal by detecting a bit modulation at a second zero crossing of the mains signal after a bit modulation at a first zero crossing of the mains signal and by detecting a bit modulation at a third zero crossing of the mains signal before a bit modulation at the fourth zero crossing indicating a one bit binary number;

(d) a pulse detector circuit detecting pulses in the filtered signal to provide a corresponding pulsed signal including the outbound message; and

wherein the two-dimensional digital demodulating component comprises a controller demodulating the corresponding pulsed signal by detecting a pulse at a second zero crossing of the mains signal after a pulse at a first zero crossing of the mains signal and by detecting a pulse at a third zero crossing of the mains signal before a pulse at the fourth zero crossing indicating a one bit binary number;

(e) the two-dimensional digital demodulating component comprises a digital processor demodulating the corresponding digitized signal by detecting a bit modulation at a third zero crossing of the mains signal after a bit modulation at a second zero crossing of the mains signal and by detecting a bit modulation at a third zero crossing of the mains signal before a bit modulation at the fourth zero crossing indicating a two bit binary number;

and wherein the digital processor demodulates the corresponding digitized signal by detecting a bit modulation at a second zero crossing of the mains signal after a bit modulation at a first zero crossing of the mains signal and by detecting a bit modulation at a fourth zero crossing of the mains signal before the “

0”

bit modulation at the first zero crossing; and

(f) a pulse detector circuit detecting pulses in the filtered signal to provide a corresponding pulsed signal including the outbound message; and

wherein the two-dimensional digital demodulating component comprises a controller demodulating the corresponding pulsed signal by detecting a pulse at a third zero crossing of the mains signal after a pulse at a second zero crossing of the mains signal and by detecting a pulse at a third zero crossing of the mains signal before a pulse at the fourth zero crossing indicating a two bit binary number; and

wherein the controller demodulates the corresponding pulsed signal by detecting a pulse at a second zero crossing of the mains signal after a pulse at a first zero crossing of the mains signal and by detecting a pulse at a fourth zero crossing of the mains signal before the “

0”

pulse at the first zero crossing.

3. The receiver of claim 1 wherein the filter component comprises:

a carrier notch filter receiving the analog outbound signal and canceling the carrier signal to provide an analog message signal; and

a low-pass filter (LPF) component receiving the analog outbound signal and filtering the analog outbound signal to provide a filtered analog outbound signal;

and wherein the A/D converter comprises;

a first A/D converter digitizing the analog message signal into a digitized message signal, and

a second A/D converter digitizing the filtered analog outbound signal and providing a digital filtered signal.

4. The receiver of claim 3 wherein the digital processor includes a buffering component comprising:

a buffer receiving the digitized message signal and sequentially providing a half-cycle buffered signal corresponding thereto, and

a phase locked loop (PLL) component receiving the digitized filtered signal and providing a half-cycle synchronization signal corresponding thereto, said half-cycle synchronization signal sampling the half-cycle buffered signal to provide a corresponding digital signal.

5. The receiver of claim 4 wherein the digital preprocessor component comprises:

a fast Fourier transform (FFT) component receiving the corresponding digital signal and providing a frequency domain signal corresponding to the digital signal; and

a dimension reduction component connected to the FFT component for receiving the frequency domain signal, said dimension reduction component providing a discretization signal corresponding to the digital signal with reduced resolution.

6. In a two-way automatic communications system (TWACS) used by an electrical utility in which outbound messages are sent from the utility to a consumer and inbound messages are sent from the consumer to the utility, the respective outbound and inbound messages being sent and received over the utility'"'"'s power distribution system, the respective outbound and inbound messages being modulated on a mains signal of the power distribution system, a receiver for detecting the outbound messages, said receiver comprising:

an analog filter component receiving an outbound signal including an outbound message to provide a filtered signal including the outbound message; and

a detecting circuit receiving the filtered signal including the outbound message to provide a corresponding signal including the outbound message; and

a demodulator for demodulating the corresponding signal by detecting at least two modulations every two cycles of the mains signal by detecting a bit modulation at a zero crossing of the mains signal relative to a half-cycle delay of a bit modulation at a another zero crossing of the mains signal.

7. The receiver of claim 6 wherein the detecting circuit comprises an A/D converter converting the filtered signal to a corresponding digitized signal and providing the corresponding digitized signal;

and

wherein the demodulator comprises a digital processor demodulating the corresponding digitized signal by detecting a bit modulation at a third zero crossing of the mains signal after a bit modulation at a second zero crossing of the mains signal and by detecting a bit modulation at a third zero crossing of the mains signal before a bit modulation at the fourth zero crossing indicating a two bit binary number.

8. The receiver of claim 6 wherein the detecting circuit comprises a bit modulation detector circuit detecting bit modulations in the filtered signal to provide a corresponding pulsed signal including the outbound message;

and

wherein the demodulator comprises a controller demodulating the corresponding pulsed signal by detecting a pulse at a third zero crossing of the mains signal after a pulse at a second zero crossing of the mains signal and by detecting a pulse at a third zero crossing of the mains signal before a pulse at the fourth zero crossing indicating a two bit binary number.

9. The receiver of claim 6 wherein the detecting circuit comprises an A/D converter converting the filtered signal to a corresponding digitized signal and providing the corresponding digitized signal;

and

wherein the demodulator comprises a digital processor demodulating the corresponding digitized signal by detecting a bit modulation at a second zero crossing of the mains signal after a bit modulation at a first zero crossing of the mains signal and by detecting a bit modulation at a third zero crossing of the mains signal before a bit modulation at the fourth zero crossing indicating a one bit binary number.

10. The receiver of claim 6 wherein the detecting circuit comprises a pulse detector circuit detecting pulses in the filtered signal to provide a corresponding pulsed signal including the outbound message;

and

wherein the demodulator comprises a controller demodulating the corresponding pulsed signal by detecting a pulse at a second zero crossing of the mains signal after a pulse at a first zero crossing of the mains signal and by detecting a pulse at a third zero crossing of the mains signal before a pulse at the fourth zero crossing indicating a one bit binary number.

11. The receiver of claim 6 wherein the detecting circuit comprises an A/D converter converting the filtered signal to a corresponding digitized signal and providing the corresponding digitized signal;

and

wherein the demodulator comprises a digital processor demodulating the corresponding digitized signal by detecting a bit modulation at a third zero crossing of the mains signal after a bit modulation at a second zero crossing of the mains signal and by detecting a bit modulation at a third zero crossing of the mains signal before a bit modulation at the fourth zero crossing indicating a two bit binary number; and

wherein the digital processor demodulates the corresponding digitized signal by detecting a bit modulation at a second zero crossing of the mains signal after a bit modulation at a first zero crossing of the mains signal and by detecting a bit modulation at a fourth zero crossing of the mains signal before the “

0”

bit modulation at the first zero crossing.

12. The receiver of claim 6 wherein the detecting circuit comprises a pulse detector circuit detecting pulses in the filtered signal to provide a corresponding pulsed signal including the outbound message;

and

wherein the demodulator comprises a controller demodulating the corresponding pulsed signal by detecting a pulse at a third zero crossing of the mains signal after a pulse at a second zero crossing of the mains signal and by detecting a pulse at a third zero crossing of the mains signal before a pulse at the fourth zero crossing indicating a two bit binary number; and

wherein the controller demodulates the corresponding pulsed signal by detecting a pulse at a second zero crossing of the mains signal after a pulse at a first zero crossing of the mains signal and by detecting a pulse at a fourth zero crossing of the mains signal before the “

0”

pulse at the first zero crossing.

13. A two-way automatic communications system (TWACS) used by an electrical utility comprising:

a substation transceiver configured for sending analog outbound messages from the utility to a consumer;

a transponder configured for sending inbound messages to the transceiver from the consumer to the utility, the respective outbound and inbound messages being modulated on a mains signal of the utility'"'"'s power distribution system; and

a receiver included in the transponder configured for enabling the detection of the outbound messages, said receiver comprising;

an analog filter component receiving an outbound signal including an outbound message to provide a filtered signal including the outbound message; and

a detecting circuit receiving the filtered signal including the outbound message to provide a corresponding signal including the outbound message; and

a demodulator for demodulating the corresponding signal by detecting at least two modulations every two cycles of the mains signal by detecting a bit modulation at a zero crossing of the mains signal relative to a half-cycle delay of a bit modulation at a another zero crossing of the mains signal.

14. The receiver of claim 13 wherein the detecting circuit comprises an A/D converter converting the filtered signal to a corresponding digitized signal and providing the corresponding digitized signal;

and

wherein the demodulator comprises a digital processor demodulating the corresponding digitized signal by detecting a bit modulation at a third zero crossing of the mains signal after a bit modulation at a second zero crossing of the mains signal and by detecting a bit modulation at a third zero crossing of the mains signal before a bit modulation at the fourth zero crossing indicating a two bit binary number.

15. The receiver of claim 13 wherein the detecting circuit comprises a bit modulation detector circuit detecting bit modulations in the filtered signal to provide a corresponding pulsed signal including the outbound message;

and

wherein the demodulator comprises a controller demodulating the corresponding pulsed signal by detecting a pulse at a third zero crossing of the mains signal after a pulse at a second zero crossing of the mains signal and by detecting a pulse at a third zero crossing of the mains signal before a pulse at the fourth zero crossing indicating a two bit binary number.

16. The receiver of claim 13 wherein the detecting circuit comprises an A/D converter converting the filtered signal to a corresponding digitized signal and providing the corresponding digitized signal;

and

wherein the demodulator comprises a digital processor demodulating the corresponding digitized signal by detecting a bit modulation at a second zero crossing of the mains signal after a bit modulation at a first zero crossing of the mains signal and by detecting a bit modulation at a third zero crossing of the mains signal before a bit modulation at the fourth zero crossing indicating a one bit binary number.

17. The receiver of claim 13 wherein the detecting circuit comprises a pulse detector circuit detecting pulses in the filtered signal to provide a corresponding pulsed signal including the outbound message;

and

wherein the demodulator comprises a controller demodulating the corresponding pulsed signal by detecting a pulse at a second zero crossing of the mains signal after a pulse at a first zero crossing of the mains signal and by detecting a pulse at a third zero crossing of the mains signal before a pulse at the fourth zero crossing indicating a one bit binary number.

18. The receiver of claim 13 wherein the detecting circuit comprises an A/D converter converting the filtered signal to a corresponding digitized signal and providing the corresponding digitized signal;

and

wherein the demodulator comprises a digital processor demodulating the corresponding digitized signal by detecting a bit modulation at a third zero crossing of the mains signal after a bit modulation at a second zero crossing of the mains signal and by detecting a bit modulation at a third zero crossing of the mains signal before a bit modulation at the fourth zero crossing indicating a two bit binary number; and

wherein the digital processor demodulates the corresponding digitized signal by detecting a bit modulation at a second zero crossing of the mains signal after a bit modulation at a first zero crossing of the mains signal and by detecting a bit modulation at a fourth zero crossing of the mains signal before the “

0”

bit modulation at the first zero crossing.

19. The receiver of claim 13 wherein the detecting circuit comprises a pulse detector circuit detecting pulses in the filtered signal to provide a corresponding pulsed signal including the outbound message;

and

wherein the demodulator comprises a controller demodulating the corresponding pulsed signal by detecting a pulse at a third zero crossing of the mains signal after a pulse at a second zero crossing of the mains signal and by detecting a pulse at a third zero crossing of the mains signal before a pulse at the fourth zero crossing indicating a two bit binary number; and

wherein the controller demodulates the corresponding pulsed signal by detecting a pulse at a second zero crossing of the mains signal after a pulse at a first zero crossing of the mains signal and by detecting a pulse at a fourth zero crossing of the mains signal before the “

0”

pulse at the first zero crossing.

20. A two-way automatic communications system (TWACS) used by an electrical utility comprising:

a substation transceiver configured for sending analog outbound messages from the utility to a consumer;

a transponder configured for sending inbound messages to the transceiver from the consumer to the utility, the respective outbound and inbound messages being modulated on a mains signal of the utility'"'"'s power distribution system; and

a receiver included in the transponder configured for enabling the detection of the outbound messages, said receiver comprising;

an analog filter component receiving the analog outbound signal including an outbound message to provide a filtered signal;

an A/D converter converting the filtered signal to a corresponding digitized signal and providing the corresponding digitized signal; and

a digital processor executing;

a digital preprocessor component receiving the corresponding digitized signal, preprocessing the received corresponding digitized signal to provide a preprocessed digital signal; and

a digital symbol determination component receiving the preprocessed digital signal and a two-dimensional digital demodulating component for digitally demodulating the received preprocessed digital signal to provide the outbound message wherein the symbol determination component comprises;

a digital preamble detector component for receiving the preprocessed digital signal and providing a symbol synchronization signal and a weight vector w corresponding to the preprocessed digital signal; and

a digital symbol estimator component for receiving the preprocessed digital signal and for receiving the weight vector w to provide a noise product signal which is;

(1) selectively sampled by the synchronization signal to provide a first dimension γ

₁ of the outbound message, and

(2) delaying by a one-half cycle multiple (z<sup>−

2</sup>) and selectively sampled by the synchronization signal to provide a second dimension γ

₂ of the outbound message, wherein the first and second dimensions γ

₁ and γ

₂ provide the outbound message.

21. The receiver of claim 20 wherein one of the following:

(a) the two-dimensional digital demodulating component comprises a digital processor demodulating the corresponding digitized signal by detecting a bit modulation at a third zero crossing of the mains signal after a bit modulation at a second zero crossing of the mains signal and by detecting a bit modulation at a third zero crossing of the mains signal before a bit modulation at the fourth zero crossing indicating a two bit binary number;

(b) a bit modulation detector circuit detects bit modulations in the filtered signal to provide a corresponding pulsed signal including the outbound message; and

wherein the two-dimensional digital demodulating component comprises a controller demodulating the corresponding pulsed signal by detecting a pulse at a third zero crossing of the mains signal after a pulse at a second zero crossing of the mains signal and by detecting a pulse at a third zero crossing of the mains signal before a pulse at the fourth zero crossing indicating a two bit binary number;

(c) the two-dimensional digital demodulating component comprises a digital processor demodulating the corresponding digitized signal by detecting a bit modulation at a second zero crossing of the mains signal after a bit modulation at a first zero crossing of the mains signal and by detecting a bit modulation at a third zero crossing of the mains signal before a bit modulation at the fourth zero crossing indicating a one bit binary number;

(d) a pulse detector circuit detecting pulses in the filtered signal to provide a corresponding pulsed signal including the outbound message; and

wherein the two-dimensional digital demodulating component comprises a controller demodulating the corresponding pulsed signal by detecting a pulse at a second zero crossing of the mains signal after a pulse at a first zero crossing of the mains signal and by detecting a pulse at a third zero crossing of the mains signal before a pulse at the fourth zero crossing indicating a one bit binary number;

(e) the two-dimensional digital demodulating component comprises a digital processor demodulating the corresponding digitized signal by detecting a bit modulation at a third zero crossing of the mains signal after a bit modulation at a second zero crossing of the mains signal and by detecting a bit modulation at a third zero crossing of the mains signal before a bit modulation at the fourth zero crossing indicating a two bit binary number;

and wherein the digital processor demodulates the corresponding digitized signal by detecting a bit modulation at a second zero crossing of the mains signal after a bit modulation at a first zero crossing of the mains signal and by detecting a bit modulation at a fourth zero crossing of the mains signal before the “

0”

bit modulation at the first zero crossing; and

(f) a pulse detector circuit detecting pulses in the filtered signal to provide a corresponding pulsed signal including the outbound message; and

wherein the two-dimensional digital demodulating component comprises a controller demodulating the corresponding pulsed signal by detecting a pulse at a third zero crossing of the mains signal after a pulse at a second zero crossing of the mains signal and by detecting a pulse at a third zero crossing of the mains signal before a pulse at the fourth zero crossing indicating a two bit binary number; and

wherein the controller demodulates the corresponding pulsed signal by detecting a pulse at a second zero crossing of the mains signal after a pulse at a first zero crossing of the mains signal and by detecting a pulse at a fourth zero crossing of the mains signal before the “

0”

pulse at the first zero crossing.

22. The receiver of claim 20 wherein the filter component comprises:

a carrier notch filter receiving the analog outbound signal and canceling the carrier signal to provide an analog message signal; and

a low-pass filter (LPF) component receiving the analog outbound signal and filtering the analog outbound signal to provide a filtered analog outbound signal;

and wherein the A/D converter comprises;

a first A/D converter digitizing the analog message signal into a digitized message signal;

and a second A/D converter digitizing the filtered analog outbound signal and providing a digital filtered signal.

23. The receiver of claim 22 wherein the digital processor includes a buffering component comprising:

a buffer receiving the digitized message signal and sequentially providing a half-cycle buffered signal corresponding thereto, and

a phase locked loop (PLL) component receiving the digitized filtered signal and providing a half-cycle synchronization signal corresponding thereto, said half-cycle synchronization signal sampling the half-cycle buffered signal to provide a corresponding digital signal.

24. The receiver of claim 23 wherein the digital preprocessor component comprises:

a fast Fourier transform (FFT) component receiving the corresponding digital signal and providing a frequency domain signal corresponding to the digital signal; and

a dimension reduction component connected to the FFT component for receiving the frequency domain signal, said dimension reduction component providing a discretization signal corresponding to the digital signal with reduced resolution.

25. In a two-way automatic communications system (TWACS) used by an electrical utility in which analog outbound messages are sent from the utility to a consumer and inbound messages are sent from the consumer to the utility, the respective outbound and inbound messages being modulated on a mains signal of the utility'"'"'s power distribution system, a method for detecting the outbound messages comprising:

receiving the analog outbound signal including an outbound message;

converting the received analog outbound signal to a corresponding digitized signal;

preprocessing the corresponding digitized signal to provide a preprocessed digital signal; and

digitally demodulating the preprocessed digital signal in two dimensions to provide the outbound message wherein the demodulating comprises;

receiving the preprocessed digital signal and providing a symbol synchronization signal and a weight vector w corresponding to the preprocessed digital signal; and

receiving the preprocessed digital signal and receiving the weight vector to provide a noise product signal which is;

(1 ) selectively sampled by the synchronization signal to provide a first dimension γ

₁ of the outbound message, and

(2 ) delayed by a one-half cycle multiple (z<sup>−

2</sup>) and selectively sampled by the synchronization signal to provide a second dimension γ

₂ of the outbound message, wherein the first and second dimensions γ

₁ and γ

₂ provide the outbound message.

26. In a two-way automatic communications system (TWACS) used by an electrical utility in which analog outbound messages are sent from the utility to a consumer and inbound messages are sent from the consumer to the utility, the respective outbound and inbound messages being modulated on a mains signal of the utility'"'"'s power distribution system, a method for detecting the outbound messages comprising:

receiving an outbound signal including an outbound message to provide a filtered signal including the outbound message; and

receiving the filtered signal including the outbound message to provide a corresponding signal including the outbound message; and

demodulating the corresponding signal by detecting at least two modulations every two cycles of the mains signal wherein the demodulating comprises;

receiving the preprocessed digital signal and providing a symbol synchronization signal and a weight vector w corresponding to the preprocessed digital signal; and

receiving the preprocessed digital signal and receiving the weight vector to provide a noise product signal which is;

(1) selectively sampled by the synchronization signal to provide a first dimension γ

₁ of the outbound message, and

(2) delayed by a one-half cycle multiple (z<sup>−

2</sup>) and selectively sampled by the synchronization signal to provide a second dimension γ

₂ of the outbound message, wherein the first and second dimensions γ

₁ and γ

₂ provide the outbound message.