Reduced state sequence estimation with soft decision outputs
First Claim
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1. A system comprising:
- signal processing circuitry and sequence estimation circuitry, wherein;
said signal processing circuitry is operable to receive a signal resulting from a transmitted plurality of symbols, each of said plurality of symbols corresponding to a plurality of subwords;
said signal processing circuitry is operable to output samples of said received signal to said sequence estimation circuitry;
said sequence estimation circuitry is operable to process said samples to generate a plurality of vectors, where each of said plurality of vectors represents a hypothesis as to the values of said plurality of symbols; and
said sequence estimation circuitry is operable to generate soft-decisions as to values of said plurality of symbols and/or values of said plurality of subwords based on a count of occurrences of a particular symbol value and/or particular subword value in said plurality of vectors.
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Abstract
A receiver may be operable to receive an inter-symbol correlated (ISC) signal, and generate a plurality of soft decisions as to information carried in the ISC signal. The soft decisions may be generated using a reduced-state sequence estimation (RSSE) process. The RSSE process may be such that the number of symbol survivors retained after each iteration of the RSSE process is less than the maximum likelihood state space. The plurality of soft decisions may comprise a plurality of log likelihood ratios (LLRs). Each of the plurality of LLRs may correspond to a respective one of a plurality of subwords of a forward error correction (FEC) codeword.
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20 Claims
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1. A system comprising:
signal processing circuitry and sequence estimation circuitry, wherein; said signal processing circuitry is operable to receive a signal resulting from a transmitted plurality of symbols, each of said plurality of symbols corresponding to a plurality of subwords; said signal processing circuitry is operable to output samples of said received signal to said sequence estimation circuitry; said sequence estimation circuitry is operable to process said samples to generate a plurality of vectors, where each of said plurality of vectors represents a hypothesis as to the values of said plurality of symbols; and said sequence estimation circuitry is operable to generate soft-decisions as to values of said plurality of symbols and/or values of said plurality of subwords based on a count of occurrences of a particular symbol value and/or particular subword value in said plurality of vectors. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10)
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11. A method comprising:
performing in a receiver comprising signal processing circuitry and sequence estimation circuitry; receiving, by said signal processing circuitry, an signal resulting from a transmitted plurality of symbols, each of said plurality of symbols corresponding to a plurality of subwords; outputting, by said signal processing circuitry, samples of said received signal to said sequence estimation circuitry; processing, by said sequence estimation circuitry, said samples to generate a plurality of vectors, where each of said plurality of vectors represents a hypothesis as to the values of said plurality of symbols; and generating, by said sequence estimation circuitry, soft-decisions as to values of said plurality of symbols and/or values of said plurality of subwords based on a count of occurrences of a particular symbol value and/or subword value in said plurality of vectors. - View Dependent Claims (12, 13, 14, 15, 16, 17, 18, 19, 20)
Specification