Circuits and methods for measuring circuit elements in an integrated circuit device

• US 9,297,850 B1
• Filed: 09/15/2014
• Issued: 03/29/2016
• Est. Priority Date: 12/23/2011
• Status: Expired due to Fees

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Clark, Lawrence T., Roy, Richard S.
• Primary Examiner(s): YOHA, CONNIE C
• Application Number:
  US14/487,053
• Time in Patent Office: 561 Days
• Field of Search: 365/189.02, 365/201, 365/198, 365/185.21
• US Class Current: 1/1
• CPC Class Codes: G01R 31/2607 Circuits therefor G01R31/2642 takes precedence
• CPC Class Codes: G01R 31/275 for testing individual semiconductor components within integrated circuits
• CPC Class Codes: G01R 35/00 Testing or calibrating of apparatus covered by the other groups of this subclass
• CPC Class Codes: G11C 11/41 forming static cells with positive feedback, i.e. cells not needing refreshing or charge regeneration, e.g. bistable multivibrator or Schmitt trigger
• CPC Class Codes: G11C 29/026 in sense amplifiers
• CPC Class Codes: G11C 29/1201 comprising I/O circuitry
• CPC Class Codes: G11C 29/48 Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
• CPC Class Codes: G11C 7/1006 Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
• CPC Class Codes: G11C 7/1051 Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits

Abstract

A memory test method is disclosed that can include providing at least one first switch of at least one test element coupled to a first memory section between a first node within a tested section and an intermediate node, coupling a test switch of the test element between the intermediate node and a forced voltage node, and coupling a second switch of the test element between the intermediate node and a second node; wherein the forced voltage node receives a forced voltage substantially the same as a voltage applied to the second node, and the second node is coupled to at least a second memory section.

Claims

1. A memory test method, comprising:

providing at least one first switch of at least one test element coupled to a first memory section between a first node within a tested section and an intermediate node,

coupling a test switch of the test element between the intermediate node and a forced voltage node, and

coupling a second switch of the test element between the intermediate node and a second node;

wherein

the forced voltage node receives a forced voltage substantially the same as a voltage applied to the second node, and the second node is coupled to at least a second memory section.

2. The memory test method of claim 1, wherein:

the test element operates in a first mode, in which the at least one first switch is configured to provide a low impedance path and the test switch is configured to provide a high impedance path; and

the test element operates in a second mode, in which the at least one first switch is configured to provide a high impedance path and the test switch is configured to provide a low impedance path.

3. The memory test method of claim 1, wherein:

the at least one first switch, test switch, and second switch each comprise transistors of different conductivity types having current paths arranged in parallel with one another.

4. The memory test method of claim 1, wherein:

the at least one first switch, test switch, and second switch each comprise at least one transistor; and

the test element fits within no more than three transistor pitches.

5. The memory test method of claim 1, wherein:

the at least one first switch includes a plurality of first parallel switches, each first parallel switch being coupled between a node of the integrated circuit and the intermediate node;

the test element is operable in a first mode in which the test switch is configured to provide a high impedance path, at least one of the parallel switches is configured to provide a low impedance path, and the first parallel switches other than the at least one parallel switch are configured to provide a high impedance path; and

the test element is operable in a second mode in which the test switch is configured to provide a low impedance path and the first parallel switches are configured to provide high impedance states.

6. The memory test method of claim 1, wherein:

the first memory section comprises a memory array;

the test element is formed in a same integrated circuit substrate having the second memory section which comprises a plurality of conductive input/output (I/O) pads formed thereon for making electrical connections to the memory circuit device; and

the forced voltage node is coupled to at least one of the I/O pads.

7. The memory test method of claim 1, further including:

the first memory section comprises a memory array; and

a column multiplexer (MUX) circuit coupled between the test element and a bit line of the memory array, the column MUX coupling the bit line to the test element in response to column address data.

8. The memory test method of claim 1, further including:

the first memory section comprises a memory array;

sense amplifiers configured to amplify electrical signals on a bit line of the memory array to generate read output data; and

the test element further includes the at least one first switch being coupled to the bit line via a sense amplifier input.

9. The memory test method of claim 1, further including:

the first memory section comprises a memory array formed from a plurality of banks, each bank including a plurality of bit lines;

wherein

the test element is coupled to one of the bit lines and further to the second memory section having at least one bank input/output (I/O) node.

10. The memory test method of claim 9, wherein:

each bank includes at least one test element coupled to the bit lines of the bank and a bank I/O node of the bank; and

a bank select circuit configured to couple each bank I/O node to a common bank node.

11. The memory test method of claim 2, further including:

the first memory section comprises a memory array having a plurality of memory cells coupled to bit lines, each memory cell including

a first pair of pull-up transistors cross-coupled between two storage nodes, and

a pair of access transistors that couple each storage node to a different bit line;

a word line driver circuit coupled to enable the access transistors in a test mode; and

the at least one test element includes

a first test element for applying a test voltage on a first bit line to a control terminal of one of the pull-up transistors of the first pair through a first of the access transistors in the test mode, the first test element operable in the first mode, and

a second test element enabling a current drawn by the one pull-up transistor to flow through a second bit line and a second of the access transistors in the test mode, the second test element operable in the first mode.

12. The memory test method of claim 11, further including:

at least one of the memory cells further includes a second pair of pull-down transistors, cross-coupled between the two storage nodes and source node; and

a source driver circuit that drives the source node to the test voltage in the test mode.

13. The memory test method of claim 1, wherein:

the first memory section comprises a memory array having a memory cell coupled to a bit line, the memory cell including

a pair of pull-up transistors cross-coupled between two storage nodes,

a pair of latching transistors cross-coupled between the two storage nodes, and

a pair of access transistors that coupled each storage node to a different bit line;

a word line driver circuit coupled to apply a test voltage to the control terminals of the access transistors in a test mode; and

the at least one test element includes

a first test element for applying an enable voltage to a control terminal of a first of the pull-up transistors through a first bit line and a first of the access transistors in the test mode, the test element operable in the first mode, and

a second test element enabling a current drawn by one of the latching transistors to flow a second bit line and latching second of the access transistors in the test mode, the second test element operable in the first mode.

14. The memory test method of claim 1, wherein at least one of the first and second memory sections comprises a static random access memory (SRAM) array.

15. A memory test method, comprising:

providing a plurality of memory sections, each including a plurality of memory cells; and

coupling a plurality of test elements between at least a first memory section and a second memory section, with the test elements

coupling at least one first switch between a first node within the first memory section and an intermediate node;

coupling a test switch between the intermediate node and a forced voltage node; and

coupling a second switch between the intermediate node and a second node within the second memory section;

wherein

the forced voltage node receives a forced voltage substantially the same as a voltage applied to the second node.

16. The memory test method of claim 15, wherein:

each memory section comprises a bank; and

each test element has a first node coupled to bit lines of a first bank and a second node coupled to a second bank.

17. The memory test method of claim 15, wherein:

each memory section comprises bank having at least one bank input/output (I/O) node; and

each test element has a first node coupled to a bank I/O node.