Distributed management of a shared clock source to a multi-core microprocessor

• US 9,298,212 B2
• Filed: 12/30/2013
• Issued: 03/29/2016
• Est. Priority Date: 12/22/2010
• Status: Active Grant

• Current Assignee: VIA Technologies Incorporated (VIA Technologies)
• Original Assignee: VIA Technologies Incorporated (VIA Technologies)
• Inventors: Gaskins, Darius D., Henry, G. Glenn
• Primary Examiner(s): Patel, Nimesh G
• Application Number:
  US14/143,666
• Publication Number:
  US 20140164816A1
• Time in Patent Office: 820 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 1/06 Clock generators producing several clock signals G06F1/08 - G06F1/14 take precedence
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Microprocessors are provided with decentralized logic and associated methods for indicating power related operating states, such as desired voltages and frequency ratios, to shared microprocessor power resources such as a voltage regulator module (VRM) and phase locked loops (PLLs). Each core is configured to generate a value to indicate a desired operating state of the core. Each core is also configured to receive a corresponding value from each other core sharing the applicable resource, and to calculate a composite value compatible with the minimal needs of each core sharing the applicable resource. Each core is further configured to conditionally drive the composite value off core to the applicable resource based on whether the core is designated as a master core for purposes of controlling or coordinating the applicable resource. The composite value is supplied to the applicable shared resource without using any active logic outside the plurality of cores.

Claims

1. A microprocessor, comprising:

a plurality of dies, each die comprising;

a plurality of cores; and

a phase-locked loop (PLL), having a frequency ratio input, wherein the PLL is configured to generate a core clock signal for provision to each of the plurality of cores of the die, wherein the core clock signal has a frequency that is a ratio of a frequency of a bus clock signal received by the microprocessor based on a value of the frequency ratio input;

wherein each core is configured to generate a first frequency ratio value that indicates the desired frequency ratio of the core and to receive the first frequency ratio value from the other cores of its die and to generate a second frequency ratio value which is the largest of the first frequency ratio values of all the cores of the die; and

wherein each core is configured to provide the second frequency ratio value to the PLL if the core is a master core of the die and to provide a zero value to the PLL if the core is not a master core of the die.

2. The microprocessor of claim 1, wherein the second frequency ratio value from the master core and the zero values from the non-master cores are wire-OR'"'"'ed together to generate the resultant frequency ratio input value to the PLL.

3. The microprocessor of claim 1, wherein each core comprises:

a fuse that indicates whether the core is the master core of the die.

4. The microprocessor of claim 1, wherein each die comprises:

inter-core wires configured to convey the first frequency ratio values between the cores of the die.

5. The microprocessor of claim 1, wherein each of the PLL frequency ratio input values is generated by the microprocessor without any active logic outside the plurality of cores.

6. A method for operating a microprocessor comprising a plurality of dies each comprising a plurality of cores and a phase-locked loop (PLL) having a frequency ratio input, wherein the PLL is configured to generate a core clock signal for provision to each of the plurality of cores of the die, wherein the core clock signal has a frequency that is a ratio of a frequency of a bus clock signal received by the microprocessor based on a value of the frequency ratio input, the method comprising:

generating, by each core, a first frequency ratio value that indicates the desired frequency ratio of the core;

receiving, by each core, the first frequency ratio value from the other cores of the core'"'"'s die;

generating a second frequency ratio value which is the largest of the first frequency ratio values of all the cores of the die; and

providing, by each core, the second frequency ratio value to the PLL, if the core is a master core of the die and otherwise providing a zero value to the PLL.

7. The method of claim 6, further comprising:

wire-OR'"'"'ing together the second frequency ratio value from the master core and the zero values from the non-master cores are to generate a resultant frequency ratio input value to the PLL.

8. The method of claim 6, wherein each core comprises:

indicating, via a fuse of each core, whether the core is the master core of the die.

9. The method of claim 6, further comprising:

conveying the first frequency ratio values between the cores of the die via inter-core wires.

10. The method of claim 6, wherein each of the PLL frequency ratio input values is generated by the microprocessor without any active logic outside the plurality of cores.

11. A computer program product encoded in at least one non-transitory computer usable medium for use with a computing device, the computer program product comprising:

computer usable program code embodied in said medium, for specifying a microprocessor, the computer usable program code comprising;

program code for specifying a plurality of dies, each die comprising;

a plurality of cores; and

a phase-locked loop (PLL), having a frequency ratio input, wherein the PLL is configured to generate a core clock signal for provision to each of the plurality of cores of the die, wherein the core clock signal has a frequency that is a ratio of a frequency of a bus clock signal received by the microprocessor based on a value of the frequency ratio input;

wherein each core is configured to generate a first frequency ratio value that indicates the desired frequency ratio of the core and to receive the first frequency ratio value from the other cores of its die and to generate a second frequency ratio value which is the largest of the first frequency ratio values of all the cores of the die; and

wherein each core is configured to provide the second frequency ratio value to the PLL if the core is a master core of the die and to provide a zero value to the PLL if the core is not a master core of the die.

12. The computer program product of claim 11, wherein the second frequency ratio value from the master core and the zero values from the non-master cores are wire-OR'"'"'ed together to generate the resultant frequency ratio input value to the PLL.

13. The computer program product of claim 11, wherein each core comprises:

a fuse that indicates whether the core is the master core of the die.

14. The computer program product of claim 11, wherein each die comprises:

inter-core wires configured to convey the first frequency ratio values between the cores of the die.

15. The computer program product of claim 11, wherein each of the PLL frequency ratio input values is generated by the microprocessor without any active logic outside the plurality of cores.

16. The computer program product of claim 11, wherein the at least one non-transitory computer usable medium is selected from the set of a disk, tape, or other magnetic, optical, or electronic storage medium.