Profiling application code to identify code portions for FPGA implementation

• US 9,298,438 B2
• Filed: 06/20/2012
• Issued: 03/29/2016
• Est. Priority Date: 06/20/2012
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Nightingale, Edmund B., LaMacchia, Brian A.
• Primary Examiner(s): PATEL, HIREN P
• Application Number:
  US13/528,251
• Publication Number:
  US 20130346979A1
• Time in Patent Office: 1,378 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 21/76 in application-specific integrated circuits [ASIC] or field-programmable devices, e.g. field-programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/00 Computer-aided design [CAD]
• CPC Class Codes: G06F 30/327 Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/343 Logical level
• CPC Class Codes: G06F 8/456 Parallelism detection
• CPC Class Codes: G06F 8/54 Link editing before load time
• CPC Class Codes: G06F 9/44 Arrangements for executing specific programs

Abstract

Application code is analyzed to determine if a hardware library could accelerate its execution. In particular, application code can be analyzed to identify calls to application programming interfaces (APIs) or other functions that have a hardware library implementation. The code can be analyzed to identify the frequency of such calls. Information from the hardware library can indicate characteristics of the library, such as its size, power consumption and FPGA resource usage. Information about the execution pattern of the application code also can be useful. This information, along with information about other concurrent processes using the FPGA resources, can be used to select a hardware library to implement functions called in the application code.

Claims

1. A computer-implemented process, the process comprising:

receiving, into memory, computer program code including references to one or more libraries;

accessing, with a computer processor, information about available hardware libraries;

determining, with a computer processor, whether the references in the computer program code can be implemented using one or more of the available hardware libraries;

generating a profile of the computer program code to predict functionality suited for execution on a field programmable gate array (FPGA) based at least in part upon the references to one or more libraries and information about the available hardware libraries including code size, power consumption data, resource data, and information about the frequency of calls made to the available hardware libraries;

receiving information from a scheduler including each of the computer program code performance requirements, priority of the computer program code execution, availability of a corresponding software library if a particular functional unit is not available within the FPGA, and context switching costs, and receiving data about an execution pattern from a prior execution of the computer program code; and

based at least in part upon the generated profile, the information received from the scheduler and the received data, selecting and loading one or more of the one or more of the available hardware libraries into the FPGA for access by an application using the computer program code.

2. The computer-implemented process of claim 1, wherein the selecting includes determining whether resources in the FPGA are available for execution of the one or more of the available hardware libraries.

3. The computer-implemented process of claim 1, wherein the selecting includes considering access to the field programmable gate array by concurrent processes.

4. The computer-implemented process of claim 1, wherein the selecting includes considering resource usage of the one or more of the available hardware libraries in the field programmable gate array.

5. The computer-implemented process of claim 1, wherein the determining and the selecting occur as part of a just-in-time compilation process prior to executing the computer program code.

6. The computer-implemented process of claim 1, wherein the determining and the selecting occur at compile time.

7. A system comprising:

one or more computer processors;

one or more computer readable hardware storage devices;

computer-executable instructions stored on the one or more computer readable hardware storage devices that, when processed by the one or more computer processors, cause the system to perform a computer-implemented process comprising;

receiving, into memory, computer program code including references to one or more libraries;

accessing, with a computer processor, information about available hardware libraries;

determining, with a computer processor, whether the references in the computer program code can be implemented using one or more of the available hardware libraries;

generating a profile of the computer program code to predict functionality suited for execution on a field programmable gate array (FPGA) based at least in part upon the references to one or more libraries and information about the available hardware libraries including code size, power consumption data, resource data, and information about the frequency of calls made to the available hardware libraries;

receiving information from a scheduler including each of the computer program code performance requirements, priority of the computer program code execution, availability of a corresponding software library if a particular functional unit is not available within the FPGA, and context switching costs, and receiving data about an execution pattern from a prior execution of the computer program code; and

based at least in part upon the generated profile, the information received from the scheduler and the received data, selecting and loading one or more of the one or more of the available hardware libraries into the FPGA for access by an application using the computer program code.

8. The system of claim 7, wherein the selecting includes determining whether resources in the field programmable gate array are available for execution of the one or more of the available hardware libraries.

9. The system of claim 7, wherein the selecting includes considering access to the field programmable gate array by concurrent processes.

10. The system of claim 7, wherein the selecting includes considering resource usage of the one or more of the available hardware libraries in the field programmable gate array.

11. The system of claim 7, wherein the determining and the selecting occur as part of a just-in-time compilation process prior to executing the computer program code.

12. The system of claim 7, wherein the determining and the selecting occur at compile time.