Building a run list for a coprocessor based on rules when the coprocessor switches from one context to another context

• US 9,298,498 B2
• Filed: 07/14/2008
• Issued: 03/29/2016
• Est. Priority Date: 02/18/2003
• Status: Active Grant

• Current Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Original Assignee: Microsoft Technology Licensing LLC (Microsoft Corporation)
• Inventors: Gosalia, Anuj B., Pronovost, Steve
• Primary Examiner(s): Kawsar, Abdullah Al
• Assistant Examiner(s): Arcos, Caroline H
• Application Number:
  US12/172,910
• Publication Number:
  US 20080301687A1
• Time in Patent Office: 2,815 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 9/30087 Synchronisation or serialisation instructions
• CPC Class Codes: G06F 9/461 Saving or restoring of program or task context
• CPC Class Codes: G06F 9/4843 by program, e.g. task dispatcher, supervisor, operating system
• CPC Class Codes: G06F 9/5016 the resource being the memory
• CPC Class Codes: G06F 9/5038 considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration scheduling strategies G06F9/4881 and subgroups
• CPC Class Codes: G06F 9/544 Buffers; Shared memory; Pipes
• CPC Class Codes: G06F 9/546 Message passing systems or structures, e.g. queues
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Techniques for minimizing coprocessor “starvation,” and for effectively scheduling processing in a coprocessor for greater efficiency and power. A run list is provided allowing a coprocessor to switch from one task to the next, without waiting for CPU intervention. A method called “surface faulting” allows a coprocessor to fault at the beginning of a large task rather than somewhere in the middle of the task. DMA control instructions, namely a “fence,” a “trap” and a “enable/disable context switching,” can be inserted into a processing stream to cause a coprocessor to perform tasks that enhance coprocessor efficiency and power. These instructions can also be used to build high-level synchronization objects. Finally, a “flip” technique is described that can switch a base reference for a display from one location to another, thereby changing the entire display surface.

Claims

1. A method for scheduling coprocessor contexts for processing in a coprocessor, comprising:

a central processing unit (CPU) generating a run list comprising a list of coprocessor contexts for processing by the coprocessor;

delivering the run list to a scheduler, the scheduler preparing the contexts on the run list for processing by the coprocessor, the coprocessor beginning to process a first context of the run list based on an order indicated in the run list;

while processing the first context, determining, by the coprocessor, that a switching event has occurred, the switching event comprising a page fault in the coprocessor processing the first context, a general protection fault in the coprocessor processing the first context, or a determination that there is not another item in the run list;

switching, by the coprocessor, to a next context in a second run list in response to the coprocessor determining that the switching event has occurred, the coprocessor switching to the next context independently of intervention from the CPU, wherein the scheduler generates the second run list based on one or more rules including;

excluding the first context of the run list from appearing in the second run list, and wherein a second context of the run list is a first context of the second run list;

signaling the CPU with a first interrupt signal based at least upon the coprocessor switching from one context in the run list to a next context in the run list, the CPU building said second run list for the coprocessor in response to the CPU receiving the first interrupt signal from the coprocessor; and

signaling the CPU with a second interrupt signal based at least upon the processor switching from the run list to the second run list, the CPU building a third run list for the coprocessor in response to the CPU receiving the second interrupt signal from the coprocessor.

2. A method according to claim 1, wherein the coprocessor is a graphics processing unit (GPU).

3. The method of claim 1,

wherein the second run list has a different order of contexts than the run list, whereby the scheduler can initiate a change in the order of contexts to be processed by the coprocessor based at least upon processing contexts in the second run list.

4. The method of claim 3, wherein the second context of the run list is placed in a location within the second run list such that the second context is not executed first within the second run list, and further comprising:

determining to include a third context of the run list in the second run list because the third context is in a location within the second run list such that the first context is executed first within the second run list.

5. The method of claim 1, further comprising:

storing information regarding a history of coprocessor switches from context to context in a specified system memory location readable by the scheduler.

6. The method of claim 5, wherein the system memory location readable by the scheduler is a history buffer available to said coprocessor only.

7. The method of claim 5, wherein the history buffer comprises sufficient memory to store at least twice the amount of information required to store the run list.

8. The method of claim 5, further comprising:

specifying a coprocessor write pointer, which indicates a location in the history buffer where the coprocessor can write new information.

9. A computer readable device, wherein the computer readable device is not a signal, comprising computer executable instructions that based at least upon execution by a computer, cause the computer to perform operations comprising:

a central processing unit (CPU) generating a run list comprising a list of coprocessor contexts for processing by a coprocessor;

delivering the run list to a scheduler, the scheduler preparing the contexts on the run list for processing by the coprocessor, the coprocessor beginning to process a first context of the run list based on an order indicated in the run list;

while processing the first context, determining, by the coprocessor, that a switching event has occurred, the switching event comprising a page fault in the coprocessor processing the first context, a general protection fault in the coprocessor processing the first context, or a determination that there is not another item in the run list;

switching, by the coprocessor, to a next context in a second run list in response to the coprocessor determining that the switching event has occurred, the coprocessor switching to the next context independently of intervention from the CPU, wherein the scheduler generates the second run list based on one or more rules including;

excluding the first context of the run list from appearing in the second run list, and wherein a second context of the run list is a first context of the second run list;

signaling the CPU with a first interrupt signal based at least upon the coprocessor switching from one context in the run list to a next context in the run list, the CPU building said second run list for the coprocessor in response to the CPU receiving the first interrupt signal from the coprocessor; and

signaling the CPU with a second interrupt signal based at least upon the processor switching from the run list to the second run list, the CPU building a third run list for the coprocessor in response to the CPU receiving the second interrupt signal from the coprocessor.

10. The computer-readable device of claim 9, further comprising computer executable instructions that based at least upon execution by the computer, cause the computer to perform operations comprising:

storing information regarding a history of coprocessor switches from context to context in a specified system memory location readable by the scheduler.

11. The computer-readable device of claim 9, wherein a system memory location readable by the scheduler is a history buffer available to said coprocessor only.

12. The computer-readable device of claim 11, wherein the history buffer comprises sufficient memory to store at least twice the amount of information required to store the run list.

13. The computer-readable device of claim 9, wherein the page fault in the coprocessor processing the first context comprises:

a page fault that occurs to a context that references an invalid ring buffer or an invalid DMA buffer.

14. A system, comprising:

a processor;

a coprocessor;

a scheduler; and

a memory communicatively coupled to the processor, the memory bearing processor-executable instructions that, based at least upon execution by the processor, cause the system at least to;

cause the processor to generate a run list comprising a list of coprocessor contexts for processing by the coprocessor;

deliver the run list to the scheduler, the scheduler preparing the contexts on the run list for processing by the coprocessor, the coprocessor beginning to process a first context of the run list based on an order indicated in the run list;

while processing the first context, determine, by the coprocessor, that a switching event has occurred, the switching event comprising a page fault in the coprocessor processing the first context, a general protection fault in the coprocessor processing the first context, or a determination that there is not another item in the run list;

switch, by the coprocessor, to a next context in a second run list in response to the coprocessor determining that the switching event has occurred, the coprocessor switching to the next context independently of intervention from the processor, wherein the scheduler generates the second run list based on one or more rules including;

excluding the first context of the run list from appearing in the second run list, and wherein a second context of the run list is a first context of the second run list;

signaling the processor with a first interrupt signal based at least upon the coprocessor switching from one context in the run list to a next context in the run list, the processor building said second run list for the coprocessor in response to the processor receiving the first interrupt signal from the coprocessor; and

signaling the processor with a second interrupt signal based at least upon the processor switching from the run list to the second run list, the processor building a third run list for the coprocessor in response to the processor receiving the second interrupt signal from the coprocessor.

15. The system of claim 14, wherein the second run list has a different order of contexts than the run list, whereby the scheduler can initiate a change in the order of contexts to be processed by the coprocessor based at least upon processing contexts in the second run list.

16. The system of claim 15, wherein the second context of the run list is placed in a location within the second run list such that the second context is not executed first within the second run list, and wherein the memory further bears processor-executable instructions that, based at least upon execution by the processor, cause the system at least to:

determine to include a third context of the run list in the second run list because the third context is in a location within the second run list such that the second context is executed first within the second run list.