Using read values from previous decoding operations to calculate soft bit information in an error recovery operation

• US 9,298,552 B2
• Filed: 09/27/2013
• Issued: 03/29/2016
• Est. Priority Date: 09/27/2013
• Status: Active Grant

• Current Assignee: SK Hynix NAND Product Solutions Corporation (SK Hynix Inc.)
• Original Assignee: Intel Corporation
• Inventors: Leem, Lark-Hoon, Guo, Xin, Motwani, Ravi H., Nelson, Scott E., Yee, Rosanna
• Primary Examiner(s): Merant, Guerrier
• Application Number:
  US14/040,554
• Publication Number:
  US 20150095736A1
• Time in Patent Office: 914 Days
• US Class Current: 1/1
• CPC Class Codes: G06F 11/1012 using codes or arrangements adapted for a specific type of error G06F11/1048 takes precedence
• CPC Class Codes: G06F 11/141 for bus or memory accesses

Abstract

Provided are an apparatus, system, and method for performing an error recovery operation with respect to a read of a block of memory cells in a storage device. A current iteration of a decoding operation is performed by applying at least one reference voltage for the current iteration to a block of the memory cells in the storage device to determine current read values in response to applying the reference voltage. A symbol is generated for each of the read memory cells by combining the determined current read value with at least one value saved during the previous iteration. The symbols are used to determine bit reliability metrics for the block of memory cells. The bit reliability metrics are decoded. In response to the decoding failing, an additional iteration of the decoding operation is performed.

Claims

1. An apparatus comprising:

a controller coupled to a storage device to perform an error recovery operation with respect to a read of a block of memory cells in the storage device, the controller to;

perform a current iteration of a decoding operation, comprising;

apply at least one reference voltage for the current iteration to the block of the memory cells in the storage device to determine current read values in response to apply the reference voltage;

generate a symbol for each of the memory cells of the block by combining a determined current read value of the determined current read values with a subset of previous read values read and saved during previous iterations of the decoding operation, wherein the subset of the previous read values is selected to maximize mutual information provided by the previous read values over possible subsets of the previous read values and the current read value;

use the symbols to determine bit reliability metrics for the block of memory cells;

decode the bit reliability metrics; and

in response to the decode failing, to perform an additional iteration of the decode operation.

2. The apparatus of claim 1, wherein the operations further comprise:

during each iteration, to decode with the current read values, wherein the operations to generate the symbols, use the symbols to determine bit reliability metrics, decode the bit reliability metrics and performing the additional iteration are only performed in response to the decode using the current read values failing.

3. The apparatus of claim 1, wherein the symbols determined during the previous iterations of the decoding operations have a same number of bits.

4. The apparatus of claim 1, wherein to combine the determined current read value with at least one previous read value for the memory cells during any previously performed iteration of the decode operations comprises to combine the current read value with all of the previous read values read during the previously performed iterations of the decode operation.

5. The apparatus of claim 1, wherein n iterations of the decode operations are performed, wherein during a first m iterations of the decode operations, where m is less than n, all the previous read values are combined with the current read value to form the symbol, and wherein during a jth iteration of the decoding operation following an mth iteration, (m−

1) of the previous read values during the previous iterations are combined with the current read value.

6. The apparatus of claim 5, wherein the operations further comprise to:

buffer the read values used during the iterations; and

use a selection criteria to select (m−

1) of the previous read values to combine with the current read value during the jth iteration of the decode operation following the mth iteration.

7. The apparatus of claim 1, wherein at least one previous read value saved from the previous iterations comprises a previous symbol generated during the previous iterations, and wherein the combine the determined current read value with the previous symbol comprises using the previous symbol and the current read value to determine the generated symbol for the current iteration.

8. The apparatus of claim 1, wherein the storage device comprises a multi level cell NAND storage.

9. The apparatus of claim 1, wherein the bit reliability metrics comprise Log Likelihood Ratio (LLR) values, and wherein the decoding uses a low density parity check (LDPC) code algorithm to decode the LLR values.

10. A method, comprising:

performing an error recovery operation with respect to a read of a block of read memory cells in a storage device; and

performing a current iteration of a decoding operation as part of the error recovery operation by;

applying at least one reference voltage for the current iteration to the block of the memory cells in the storage device to determine current read values in response to applying the reference voltage;

generating a symbol for each of the memory cells of the block by combining a determined current read value of the determined current read values with a subset of previous read values read and saved during previous iterations of the decoding operation, wherein the subset of the previous read values is selected to maximize mutual information provided by the previous read values over possible subsets of the previous read values and the current read value;

using the symbols to determine bit reliability metrics for the block of memory cells;

decoding the bit reliability metrics; and

in response to the decoding failing, performing an additional iteration of the decoding operation.

11. The method of claim 10, further comprising:

during each iteration, decoding with the current read values, wherein the generating the symbols, using the symbols to determine bit reliability metrics, decoding the bit reliability metrics and performing the additional iteration are only performed in response to the decoding using the current read values failing.

12. The method of claim 10, wherein the symbols determined during the previous iterations of the decoding operations have a same number of bits.

13. The method of claim 10, wherein the combining the determined current read value with at least one previous read value for the memory cells during any previously performed iteration of the decoding operations comprises combining the current read value with all of the previous read values read during the previously performed iterations of the decoding operation.

14. The method of claim 10, wherein n iterations of the decoding operations are performed, wherein during a first m iterations of the decoding operations, where m is less than n, all the previous read values are combined with the current read value to form the symbol, and wherein during a jth iteration of the decoding operation following an mth iteration, (m−

1) of the previous read values during the previous iterations are combined with the current read value.

15. The method of claim 10, wherein at least one previous read value saved from the previous iterations comprises a previous symbol generated during the previous iterations, and wherein the combining the determined current read value with the previous symbol comprises using the previous symbol and the current read value to determine the generated symbol for the current iteration.

16. The method of claim 10, wherein the bit reliability metrics comprise Log Likelihood Ratio (LLR) values, and wherein the decoding uses a low density parity check (LDPC) code algorithm to decode the LLR values.

17. A system comprising:

a processor;

a memory coupled to the processor;

a storage device, wherein data is communicated among the processor, the memory, and the storage device, comprising;

memory cells;

a controller coupled to a storage device to perform an error recovery operation with respect to a read of a block of the memory cells in the storage device to perform operations comprising;

perform a current iteration of a decoding operation, comprising;

apply at least one reference voltage for the current iteration to a block of the memory cells in the storage device to determine current read values in response to applying the reference voltage;

generate a symbol for each of the memory cells of the block by combining a determined current read value of the determined current values with a subset of previous read values read and saved during previous iterations of the decoding operation, wherein the subset of the previous read values is selected to maximize mutual information provided by the previous read values over possible subsets of the previous read values and the current read value;

use the symbols to determine bit reliability metrics for the block of memory cells;

decode the bit reliability metrics; and

in response to the decode failing, perform an additional iteration of the decode operation.

18. The system of claim 17, wherein at least one previous read value saved from the previous iterations comprises a previous symbol generated during the previous iterations, and wherein the combining the determined current read value with the previous symbol comprises using the previous symbol and the current read value to determine the generated symbol for the current iteration.

19. The system of claim 17, wherein the storage device comprises a multi level cell NAND storage.

20. The system of claim 17, wherein the bit reliability metrics comprise Log Likelihood Ratio (LLR) values, and wherein the decoding uses a low density parity check (LDPC) code algorithm to decode the LLR values.