Identifying high-conflict cache lines in transactional memory computing environments

• US 9,298,623 B2
• Filed: 09/26/2013
• Issued: 03/29/2016
• Est. Priority Date: 09/26/2013
• Status: Expired due to Fees

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: GlobalFoundries, Inc.
• Inventors: Busaba, Fadi Y., Cain, Harold W. III, Gschwind, Michael K., Michael, Maged M., Salapura, Valentina, Schwarz, Eric M., Shum, Chung-Lung K.
• Primary Examiner(s): Tsai, Henry
• Assistant Examiner(s): Hassan, Aurangzeb
• Application Number:
  US14/037,901
• Publication Number:
  US 20150089153A1
• Time in Patent Office: 915 Days
• Field of Search: None
• US Class Current: 1/1
• CPC Class Codes: G06F 12/0815 Cache consistency protocols
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 2212/1016 Performance improvement
• CPC Class Codes: G06F 2212/502 using adaptive policy
• CPC Class Codes: G06F 9/467 Transactional memory G06F9/528 takes precedence
• CPC Class Codes: G06F 9/528 by using speculative mechanisms

Abstract

Cache lines in a computing environment with transactional memory are configurable with a coherency mode and are associated with a high-conflict indicator. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. A cache line is placed in sub-line coherency mode based on examining the high-conflict indicator. A transaction accessing a memory address in a cache line in sub-line coherency mode marks only the sub-cache line portion associated with the memory address as transactionally accessed. The high-conflict indicator may be included in a set of descriptive bits associated with the cache line. A copy of the high-conflict indicator for a cache line in a first cache may be updated with the high-conflict indicator for the cache line in a second cache.

Claims

1. A method for reducing transaction conflicts in a computing environment with transactional memory, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, each cache line associated with a high-conflict indicator, the method comprising:

examining a first high-conflict indicator associated with a first cache line;

based on the examining, placing the first cache line in a sub-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode;

executing a transaction in the computing environment, the transaction accessing a memory address within the first cache line; and

accessing and managing, while executing the transaction, only a relevant sub-cache line portion of the first cache line in the sub-line coherency mode, the relevant sub-cache line portion associated with the memory address, wherein the first cache line is a first-cache copy of the first cache line in a first cache, and wherein the first high-conflict indicator is associated with the first-cache copy, the method further comprising;

determining, before executing the transaction, that a second-cache copy of the first cache line in a second cache is a high-conflict cache line;

setting a second high-conflict indicator associated with the second-cache copy; and

based on the setting the second high-conflict indicator, setting the first high-conflict indicator associated with the first-cache copy.

2. The method of claim 1, wherein the first high-conflict indicator is associated with a first cache, the method further comprising:

determining, before executing the transaction, that the first cache line is a high-conflict cache line; and

setting the first high-conflict indicator associated with the first cache line in the first cache.

3. The method of claim 1, wherein each cache line is associated with a plurality of descriptive bits, the plurality of descriptive bits including the high-conflict indicator.

4. The method of claim 1, further comprising:

determining that a reset criterion associated with the first high-conflict indicator is satisfied;

resetting the first high-conflict indicator based on the determining that the reset criterion is satisfied; and

placing the first cache line in a full-line coherency mode, wherein the cache control logic is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity, the placing based on the determining that the reset criterion is satisfied.

5. The method of claim 4, wherein the reset criterion is selected from the group consisting of:

a period of time elapses;

a number of transactions complete;

a number of instructions complete; and

the first cache line is cast out of the cache.

6. A computer system for reducing transaction conflicts in a computing environment with transactional memory, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, each cache line associated with a high-conflict indicator, the computer system comprising:

a memory; and

a processor in communication with the memory, wherein the computer system is configured to perform a method, the method comprising;

examining a first high-conflict indicator associated with a first cache line;

based on the examining, placing the first cache line in a sub-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode;

executing a transaction in the computing environment, the transaction accessing a memory address within the first cache line; and

accessing and managing, while executing the transaction, only a relevant sub-cache line portion of the first cache line in the sub-line coherency mode, the relevant sub-cache line portion associated with the memory address, wherein the first cache line is a first-cache copy of the first cache line in a first cache, and wherein the first high-conflict indicator is associated with the first-cache copy, the method further comprising;

determining, before executing the transaction, that a second-cache copy of the first cache line in a second cache is a high-conflict cache line;

setting a second high-conflict indicator associated with the second-cache copy; and

based on the setting the second high-conflict indicator, setting the first high-conflict indicator associated with the first-cache copy.

7. The computer system of claim 6, wherein each cache line is associated with a plurality of descriptive bits, the plurality of descriptive bits including the high-conflict indicator.

8. The computer system of claim 6, wherein the setting the first high-conflict indicator comprises:

casting-out the second-cache copy and the associated second high-conflict indicator from the second cache to a higher level cache; and

updating the first-cache copy and the associated first high-conflict indicator in the first cache from the higher level cache.

9. The computer system of claim 6, wherein the setting the first high-conflict indicator comprises:

requesting the second-cache copy from the second cache;

receiving the second-cache copy and the associated second high-conflict indicator from the second cache; and

installing the second-cache copy and the associated second high-conflict indicator in the first cache.

10. The computer system of claim 6, wherein the determining that the second-cache copy of the first cache line is the high-conflict cache line comprises:

incrementing a counter in a conflict address detection table associated with the second cache, the counter associated with the second-cache copy of the first cache line; and

determining that the incremented counter satisfies a high-conflict criterion.

11. The computer system of claim 6, wherein the method further comprises:

determining that a reset criterion associated with the first high-conflict indicator is satisfied;

resetting the first high-conflict indicator based on the determining that the reset criterion is satisfied; and

placing the first cache line in a full-line coherency mode, wherein the cache control logic is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity, the placing based on the determining that the reset criterion is satisfied.

12. The computer system of claim 11, wherein the reset criterion is selected from the group consisting of:

a period of time elapses;

a number of transactions complete;

a number of instructions complete; and

the first cache line is cast out of the cache.

13. A computer program product for reducing transaction conflicts in a computing environment with transactional memory, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, each cache line associated with a high-conflict indicator, the computer program product comprising:

a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method, the method comprising;

examining a first high-conflict indicator associated with a first cache line;

based on the examining, placing the first cache line in a sub-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode;

executing a transaction in the computing environment, the transaction accessing a memory address within the first cache line; and

accessing and managing, while executing the transaction, only a relevant sub-cache line portion of the first cache line in the sub-line coherency mode, the relevant sub-cache line portion associated with the memory address, wherein the first cache line is a first-cache copy of the first cache line in a first cache, and wherein the first high-conflict indicator is associated with the first-cache copy, the method further comprising;

determining, before executing the transaction, that a second-cache copy of the first cache line in a second cache is a high-conflict cache line;

setting a second high-conflict indicator associated with the second-cache copy; and

based on the setting the second high-conflict indicator, setting the first high-conflict indicator associated with the first-cache copy.

14. The computer program product of claim 13, wherein the method further comprises:

marking, while executing the transaction, only the relevant sub-cache line portion of the first cache line as transactionally accessed.

15. The computer program product of claim 13, wherein each cache line is associated with a plurality of descriptive bits, the plurality of descriptive bits including the high-conflict indicator.

16. The computer program product of claim 13, wherein the method further comprises:

determining that a reset criterion associated with the first high-conflict indicator is satisfied;

resetting the first high-conflict indicator based on the determining that the reset criterion is satisfied; and

placing the first cache line in a full-line coherency mode, wherein the cache control logic is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity, the placing based on the determining that the reset criterion is satisfied.

17. The computer program product of claim 13, wherein the method further comprises:

executing a second transaction in the computing environment, the second transaction accessing a second memory address within the first cache line;

examining, before completing the second transaction, the first high-conflict indicator associated with the first cache line;

based on the examining before completing the second transaction, discovering that the first cache line is not a high-conflict cache line;

based on the discovering that the first cache line is not a high-conflict cache line, placing the first cache line in a full-line coherency mode, wherein the cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode with a full-line granularity; and

accessing and managing, while executing the transaction, a full cache line of the first cache line in the full-line coherency mode.