Managing high-conflict cache lines in transactional memory computing environments
First Claim
1. A method for reducing transaction conflicts in a computing environment with transactional memory, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the method comprising:
- executing a first transaction in the computing environment, the first transaction including a group of instructions operating atomically on a data structure in said memory and accessing a first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode that enforces transactional semantics using a full cache line as a granularity of memory accesses to detect transaction conflicts;
detecting a conflicting access of the first cache line while executing the first transaction, the conflicting access resulting in a transactional abort;
based on the detecting, determining that the first cache line is a high-conflict cache line involved in a high number of transaction conflicts, and placing the determined high-conflict first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; and
executing a subsequent transaction including a group of instructions operating atomically on the data structure in said memory in the computing environment, the subsequent transaction accessing and managing only a relevant sub-cache line portion of the first cache line in the sub-line coherency mode.
6 Assignments
0 Petitions
Accused Products
Abstract
Cache lines in a computing environment with transactional memory are configurable with a coherency mode. Cache lines in full-line coherency mode are operated or managed with full-line granularity. Cache lines in sub-line coherency mode are operated or managed as sub-cache line portions of a full cache line. When a transaction accessing a cache line in full-line coherency mode results in a transactional abort, the cache line may be placed in sub-line coherency mode if the cache line is a high-conflict cache line. The cache line may be associated with a counter in a conflict address detection table that is incremented whenever a transaction conflict is detected for the cache line. The cache line may be a high-conflict cache line when the counter satisfies a high-conflict criterion, such as reaching a threshold value. The cache line may be returned to full-line coherency mode when a reset criterion is satisfied.
58 Citations
17 Claims
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1. A method for reducing transaction conflicts in a computing environment with transactional memory, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the method comprising:
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executing a first transaction in the computing environment, the first transaction including a group of instructions operating atomically on a data structure in said memory and accessing a first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode that enforces transactional semantics using a full cache line as a granularity of memory accesses to detect transaction conflicts; detecting a conflicting access of the first cache line while executing the first transaction, the conflicting access resulting in a transactional abort; based on the detecting, determining that the first cache line is a high-conflict cache line involved in a high number of transaction conflicts, and placing the determined high-conflict first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; and executing a subsequent transaction including a group of instructions operating atomically on the data structure in said memory in the computing environment, the subsequent transaction accessing and managing only a relevant sub-cache line portion of the first cache line in the sub-line coherency mode. - View Dependent Claims (2, 3, 4, 5)
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6. A computer system for reducing transaction conflicts in a computing environment with transactional memory, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the computer system comprising:
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a memory; and a processor in communication with the memory, wherein the computer system is configured to perform a method, the method comprising; executing a first transaction in the computing environment, the first transaction including a group of instructions operating atomically on a data structure in said memory and accessing a first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode that enforces transactional semantics using a full cache line as a granularity of memory accesses to detect transaction conflicts; detecting a conflicting access of the first cache line while executing the first transaction, the conflicting access resulting in a transactional abort; based on the detecting, determining that the first cache line is a high-conflict cache line involved in a high number of transaction conflicts, and placing the determined high-conflict first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; and executing a subsequent transaction including a group of instructions operating atomically on the data structure in said memory in the computing environment, the subsequent transaction accessing and managing only a relevant sub-cache line portion of the first cache line in the sub-line coherency mode. - View Dependent Claims (7, 8, 9, 10, 11, 12, 13)
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14. A computer program product for reducing transaction conflicts in a computing environment with transactional memory, the computing environment including a cache configured to hold a plurality of cache lines, each cache line configurable with a coherency mode, the computer program product comprising:
a non-transitory computer readable storage medium readable by a processing circuit and storing instructions for execution by the processing circuit for performing a method, the method comprising; executing a first transaction in the computing environment, the first transaction including a group of instructions operating atomically on a data structure in said memory and accessing a first cache line in a full-line coherency mode, wherein cache control logic associated with the cache is configured to operate or manage the first cache line in the full-line coherency mode that enforces transactional semantics using a full cache line as a granularity of memory accesses to detect transaction conflicts; detecting a conflicting access of the first cache line while executing the first transaction, the conflicting access resulting in a transactional abort; based on the detecting, determining that the first cache line is a high-conflict cache line involved in a high number of transaction conflicts, and placing the determined high-conflict first cache line in a sub-line coherency mode, wherein the cache control logic is configured to operate or manage a plurality of sub-cache line portions of the first cache line in the sub-line coherency mode; and executing a subsequent transaction including a group of instructions operating atomically on the data structure in said memory in the computing environment, the subsequent transaction accessing and managing only a relevant sub-cache line portion of the first cache line in the sub-line coherency mode. - View Dependent Claims (15, 16, 17)
Specification