Debugging an optimized design implemented in a device with a pre-optimized design simulation

• US 9,298,865 B1
• Filed: 03/20/2014
• Issued: 03/29/2016
• Est. Priority Date: 03/20/2014
• Status: Active Grant

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Altera Corporation (Intel Corporation)
• Inventors: Peng, Yi
• Primary Examiner(s): Siek, Vuthe
• Application Number:
  US14/220,926
• Time in Patent Office: 740 Days
• Field of Search: 716/106, 716/111, 716/112, 716/113, 716/114, 716/134, 716/136
• US Class Current: 1/1
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation

Abstract

Techniques and mechanisms debug a device implementing an optimized design using a pre-optimized design simulation. For example, data indicating interconnect in a pre-optimized design to simulate may be received. A node in common between the pre-optimized design and an optimized design may be identified. A tap at the output of the node in the optimized design may be inserted for providing data for the simulation.

Claims

1. A method for simulating a design implemented in a semiconductor device, the method comprising:

receiving first interconnect data, the first interconnect data indicating a first interconnect of a first logic design implemented within a circuit schematic, wherein the first interconnect is associated with a first combinational logic block;

identifying, by a processor, a first node for the first combinational logic block, the first node having an output providing an input to the first combinational logic block;

identifying, by the processor, a second node in a second logic design physically implemented in the semiconductor device, the second node having an output providing an input to a second combinational logic block, wherein the second combinational logic block physically implemented in the semiconductor device is a modified version of the first combinational logic block implemented within the circuit schematic, and the second node providing an input to the second combinational logic block corresponds to the first node providing an input to the first combinational logic block;

configuring the semiconductor device such that the second logic design is modified to include a tap associated with the output of the second node; and

simulating a signal associated with the first interconnect of the first logic design implemented within the circuit schematic based on data provided by the tap in the second logic design physically implemented in the semiconductor device.

2. The method of claim 1, wherein the first node and the second node are registers.

3. The method of claim 1, further comprising:

receiving second interconnect data, the second interconnect data indicating a second interconnect of the first logic design;

determining, by the processor, that the second interconnect is associated with the first node; and

simulating a signal associated with the second interconnect in the first logic design based on data provided by the tap in the second logic design.

4. The method of claim 1, wherein the simulation is further based on the first combinational logic block.

5. The method of claim 4, wherein the first interconnect is an output of the first combinational logic block.

6. The method of claim 1, wherein the data provided by the tap is provided by debug logic coupled with the tap.

7. The method of claim 1, wherein the second logic design is a modified version of the first logic design, and the second node in the second logic design corresponds to the first node in the first logic design.

8. The method of claim 7, wherein the second logic design is further mapped to resources of a device, the second node mapped to a first resource, and at least a portion of the second combinational logic block mapped to a second resource, the output of the second node associated with an interconnect between the first resource and the second resource.

9. The method of claim 1, wherein the outputs of the first node and the second node provide the same data to the combinational logic blocks.

10. The method of claim 1, wherein the second combinational logic block is an optimized version of the first combinational logic block.

11. The method of claim 1, wherein the second logic design and the first logic design implement a same functionality, and wherein the second logic design implements the same functionality in the semiconductor device with fewer logical resources than the first logic design implemented in the circuit schematic.

12. A non-transitory computer readable medium having instructions stored thereon for simulating a design implemented in a semiconductor device, the instructions executable by a processor to:

receive first interconnect data, the first interconnect data indicating a first interconnect of a first logic design implemented within a circuit schematic, wherein the first interconnect is associated with a first combinational logic block;

identify a first node for the first combinational logic block, the first node having an output providing an input to the first combinational logic block;

identify a second node in a second logic design physically implemented in the semiconductor device, the second node having an output providing an input to a second combinational logic block, wherein the second combinational logic block physically implemented in the semiconductor device is a modified version of the first combinational logic block implemented within the circuit schematic, and the second node providing an input to the second combinational logic block corresponds to the first node providing an input to the first combinational logic block;

configure the semiconductor device such that the second logic design is modified to include a tap associated with the output of the second node; and

simulate a signal associated with the first interconnect of the first logic design implemented within the circuit schematic based on data provided by the tap in the second logic design physically implemented in the semiconductor device.

13. The non-transitory computer readable medium of claim 12, wherein the first node and the second node are registers.

14. The non-transitory computer readable medium of claim 12, the instructions executable by a processor to:

receive second interconnect data, the second interconnect data indicating a second interconnect of the first logic design;

determine that the second interconnect is associated with the first node; and

simulate a signal associated with the second interconnect in the first logic design based on data provided by the tap in the second logic design.

15. The non-transitory computer readable medium of claim 12, wherein the simulation is further based on the first combinational logic block.

16. The non-transitory computer readable medium of claim 15, wherein the first interconnect is an output of the first combinational logic block.

17. The non-transitory computer readable medium of claim 12, wherein the data provided by the tap is provided by debug logic coupled with the tap.

18. The non-transitory computer readable medium of claim 12, wherein the second logic design is a modified version of the first logic design, and the second node in the second logic design corresponds to the first node in the first logic design.

19. The non-transitory computer readable medium of claim 12, wherein the second logic design is further mapped to resources of a device, the second node mapped to a first resource, and at least a portion of the second combinational logic block mapped to a second resource, the output of the second node associated with an interconnect between the first resource and the second resource.

20. The non-transitory computer readable medium of claim 12, wherein the outputs of the first node and the second node provide the same data to the combinational logic blocks.

21. The non-transitory computer readable medium of claim 12, wherein the second combinational logic block is an optimized version of the first combinational logic block.

22. One or more computing devices for simulating a design implemented in a semiconductor device, the one or more computing devices comprising:

one or more processors operable to execute one or more instructions to;

receive first interconnect data, the first interconnect data indicating a first interconnect of a first logic design implemented within a circuit schematic, wherein the first interconnect is associated with a first combinational logic block;

identify, by the processor, a first node for the first combinational logic block, the first node having an output providing an input to the first combinational logic block;

identify, by the processor, a second node in a second logic design physically implemented in the semiconductor device, the second node having an output providing an input to a second combinational logic block, wherein the second combinational logic block physically implemented in the semiconductor device is a modified version of the first combinational logic block implemented within the circuit schematic, and the second node providing an input to the second combinational logic block corresponds to the first node providing an input to the first combinational logic block;

configure semiconductor device such that the second logic design is modified to include a tap associated with the output of the second node; and

simulate a signal associated with the first interconnect of the first logic design implemented within the circuit schematic based on data provided by the tap in the second logic design physically implemented in the semiconductor device.