Write operations in spin transfer torque memory

• US 9,299,412 B2
• Filed: 02/26/2014
• Issued: 03/29/2016
• Est. Priority Date: 02/26/2014
• Status: Active Grant

• Current Assignee: Tahoe Research Limited (f/k/a Learndale Limited) (Vector Capital Corporation)
• Original Assignee: Intel Corporation
• Inventors: Naeimi, Helia, Lu, Shih-Lien L., Augustine, Charles
• Primary Examiner(s): NGUYEN, HIEN N
• Application Number:
  US14/191,191
• Publication Number:
  US 20150243335A1
• Time in Patent Office: 762 Days
• US Class Current: 1/1
• CPC Class Codes: G11C 11/1657 Word-line or row circuits
• CPC Class Codes: G11C 11/1675 Writing or programming circuits or methods
• CPC Class Codes: G11C 7/1009 Data masking during input/output

Abstract

In one embodiment, a controller comprises logic to identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state, mask write operations to the second plurality of cells in the row, set the first plurality of cells to a parallel state, mask write operations to the first plurality of cells in the row, and set the second plurality of cells to an anti-parallel state.

Claims

1. A controller comprising logic to:

identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state;

mask write operations to the second plurality of cells in the row;

set the first plurality of cells to a parallel state;

mask write operations to the first plurality of cells in the row; and

set the second plurality of cells to an anti-parallel state.

2. The controller of claim 1, further comprising logic to:

set a word line in the first plurality of cells to a parallel state write voltage, V_WR1;

set a select line in the first plurality of cells to a GND voltage; and

set a bit line in the first plurality of cells to a positive voltage, V_DD.

3. The controller of claim 2, wherein:

the positive voltage, V_DD, is to measure between 2.7 volts and 5.0 volts; and

the parallel state write voltage, V_WR1, is to measure between GND volts and −

V_DD/2 volts.

4. The controller of claim 2, further comprising logic to:

set a select line in the second plurality of cells to a voltage which is less than zero; and

set a bit line in the second plurality of cells to a voltage which is less than zero.

5. The controller of claim 1, further comprising logic to:

set a word line in the second plurality of cells to an anti-parallel state write voltage, V_WRO;

set a select line in the second plurality of cells to a GND voltage; and

set a bit line in the second plurality of cells to a negative voltage, −

V_DD.

6. The controller of claim 5, wherein:

the negative voltage, −

V_DD, is to measure between −

2.7 volts and −

5 volts; and

the anti-parallel state write voltage, V_WR0, is to measure between GND and V_DD volts.

7. The controller of claim 5, further comprising logic to:

set a select line in the second plurality of cells to a GND voltage; and

set a bit line in the second plurality of cells to a GND voltage.

8. A memory, comprising:

at least one spin-transfer torque (STT) memory device; and

a controller comprising logic to;

identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state;

mask write operations to the second plurality of cells in the row;

set the first plurality of cells to a parallel state;

mask write operations to the first plurality of cells in the row; and

set the second plurality of cells to an anti-parallel state.

9. The memory of claim 8, wherein the controller further comprises logic to:

set a word line in the first plurality of cells to a parallel state write voltage, V_WR1;

set a select line in the first plurality of cells to a GND voltage; and

set a bit line in the first plurality of cells to a positive voltage, V_DD.

10. The memory of claim 9, wherein:

the positive voltage, V_DD, is to measure between 2.7 volts and 5.0 volts; and

the parallel state write voltage, V_WR1, is to measure between GND volts and −

V_DD/2 volts.

11. The memory of claim 9, wherein the controller further comprises logic to:

set a select line in the second plurality of cells to a voltage which is less than zero; and

set a bit line in the second plurality of cells to a voltage which is less than zero.

12. The memory of claim 8, wherein the controller further comprises logic to:

set a word line in the second plurality of cells to an anti-parallel state write voltage, V_WR0;

set a select line in the second plurality of cells to a GND voltage; and

set a bit line in the second plurality of cells to a negative voltage, −

V_DD.

13. The memory of claim 12, wherein:

the negative voltage, −

V_DD, is to measure between −

2.7 volts and −

5 volts; and

the anti-parallel state write voltage, V_WR0, is to measure between GND and V_DD volts.

14. The memory of claim 12, wherein the controller further comprises logic to:

set a select line in the second plurality of cells to a GND voltage; and

set a bit line in the second plurality of cells to a GND voltage.

15. An electronic device comprising:

a processor;

at least one spin-transfer torque (STT) memory device; and

a controller comprising logic to;

identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state;

mask write operations to the second plurality of cells in the row;

set the first plurality of cells to a parallel state;

mask write operations to the first plurality of cells in the row; and

set the second plurality of cells to an anti-parallel state.

16. The electronic device of claim 15, wherein the controller further comprises logic to:

set a word line in the first plurality of cells to a parallel state write voltage, V_WR1;

set a select line in the first plurality of cells to a GND voltage; and

set a bit line in the first plurality of cells to a positive voltage, V_DD.

17. The electronic device of claim 16, wherein:

the positive voltage, V_DD, is to measure between 2.7 volts and 5.0 volts; and

the parallel state write voltage, V_WR1, is to measure between GND volts and −

V_DD/2 volts.

18. The electronic device of claim 16, wherein the controller further comprises logic to:

set a select line in the second plurality of cells to a voltage which is less than zero; and

set a bit line in the second plurality of cells to a voltage which is less than zero.

19. The electronic device of claim 15, wherein the controller further comprises logic to:

set a word line in the second plurality of cells to an anti-parallel state write voltage, V_WR0;

set a select line in the second plurality of cells to a GND voltage; and

set a bit line in the second plurality of cells to a negative voltage, −

V_DD.

20. The electronic device of claim 19, wherein:

the negative voltage, −

V_DD, is to measure between −

2.7 volts and −

5 volts; and

the anti-parallel state write voltage, V_WR0, is to measure between GND and V_DD volts.

21. The electronic device of claim 19, wherein the controller further comprises logic to:

set a select line in the second plurality of cells to a GND voltage; and

set a bit line in the second plurality of cells to a GND voltage.

22. A computer program product comprising logic instructions stored in a non-transitory computer-readable medium which, when executed by a controller, configure the controller to:

identify a first plurality of cells in a row of spin transfer torque (STT) memory which are to be set to a parallel state and a second plurality of cells in the row of the STT memory which are to be set to an anti-parallel state;

mask write operations to the second plurality of cells in the row;

set the first plurality of cells to a parallel state;

mask write operations to the first plurality of cells in the row; and

set the second plurality of cells to an anti-parallel state.

23. The computer program product of claim 22, further comprising logic instructions stored in a non-transitory computer-readable medium which, when executed by a controller, configure the controller to:

set a word line in the first plurality of cells to a parallel state write voltage, V_WR1;

set a select line in the first plurality of cells to a GND voltage; and

set a bit line in the first plurality of cells to a positive voltage, V_DD.

24. The computer program product of claim 23, wherein:

the positive voltage, V_DD, is to measure between 2.7 volts and 5.0 volts; and

the parallel state write voltage, V_WR1, is to measure between GND volts and −

V_DD/2 volts.

25. The computer program product of claim 23, further comprising logic instructions stored in a non-transitory computer-readable medium which, when executed by a controller, configure the controller to:

set a select line in the second plurality of cells to a voltage which is less than zero; and

set a bit line in the second plurality of cells to a voltage which is less than zero.