Methods for reading and programming 1-R resistive change element arrays

• US 9,299,430 B1
• Filed: 01/22/2015
• Issued: 03/29/2016
• Est. Priority Date: 01/22/2015
• Status: Active Grant

• Current Assignee: Nantero Incorporated
• Original Assignee: Nantero Incorporated
• Inventors: Bertin, Claude L., Cleveland, Lee
• Primary Examiner(s): Luu, Pho M
• Application Number:
  US14/603,037
• Time in Patent Office: 432 Days
• Field of Search: 365/163, 365/100, 365/113, 365/148
• US Class Current: 1/1
• CPC Class Codes: G11C 11/5678 using amorphous/crystalline phase transition storage elements
• CPC Class Codes: G11C 13/0004 comprising amorphous/crystalline phase transition cells
• CPC Class Codes: G11C 13/0007 comprising metal oxide memory material, e.g. perovskites
• CPC Class Codes: G11C 13/0011 comprising conductive bridging RAM [CBRAM] or programming metallization cells [PMCs]
• CPC Class Codes: G11C 13/0026 Bit-line or column circuits
• CPC Class Codes: G11C 13/0028 Word-line or row circuits
• CPC Class Codes: G11C 13/0038 Power supply circuits
• CPC Class Codes: G11C 13/004 Reading or sensing circuits or methods
• CPC Class Codes: G11C 13/0061 Timing circuits or methods
• CPC Class Codes: G11C 13/0069 Writing or programming circuits or methods
• CPC Class Codes: G11C 13/025 using fullerenes, e.g. C60, or nanotubes, e.g. carbon or silicon nanotubes
• CPC Class Codes: G11C 2013/0054 Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
• CPC Class Codes: G11C 2013/0078 Write using current through the cell
• CPC Class Codes: G11C 2213/71 Three dimensional array
• CPC Class Codes: G11C 2213/72 Array wherein the access device being a diode
• CPC Class Codes: G11C 2213/77 Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Abstract

Methods for reading and programming one or more resistive change elements within a 1-R resistive change element array are disclosed. These methods include using measurement and storage elements to measure the electrical response of one or more selected cells within an array and then comparing that stored electrical response to the electrical response of a reference element within the array to determine the resistive state of the one or more selected cells. These methods also include programming methods wherein selectable current limiting elements are used to permit or inhibit programming currents from flowing through selected and unselected cells, respectively. These methods further include programming methods that use specific biasing of array lines to provide sufficient programming currents through only selected cells.

Claims

1. A method for determining the resistive state of at least one resistive change element within a resistive change element array, comprising:

providing a resistive change element array, said resistive change element array comprising;

a plurality of word lines;

a plurality of bit lines; and

a plurality of resistive change elements, wherein each resistive change element has a first terminal and a second terminal and wherein said first terminal of each resistive change element is in electrical communication with a word line and said second terminal of each resistive change element is in electrical communication with a bit line;

a least one resistive reference element, said resistive reference element having a first terminal in electrical communication with a word line and a second terminal in electrical communication with a bit line;

initializing all of said bit lines and all of said word lines within said resistive change element array to a ground;

selecting one word line within said resistive change element array and charging said selected word line to a preselected voltage while holding all other word lines at ground and allowing all bit lines to float;

discharging said selected word line through at least one resistive change element and observing at least one discharge current through said at least one resistive change element;

re-initializing all of said bit lines and all of said word lines within said resistive change element array to a ground;

selecting at least one resistive reference element and charging the word line in electrical communication with said at least one selected resistive reference element to a preselected voltage while holding all other word lines at ground and allowing all bit lines to float;

discharging said word line in electrical communication with said at least one selected resistive reference element through said at least one selected resistive reference element and observing at least one discharge current through at least one selected resistive reference element;

comparing at least one discharge current observed through at least one of said resistive change element and at least one discharge current observed through at least one of said selected resistive reference elements to determine the resistive state of at least one resistive change element.

2. The method of claim 1 wherein the resistive state of every resistive change element in electrical communication with said selected word line is determined simultaneously.

3. The method of claim 1 wherein a discharge current observed through said resistive change element higher than a discharge current through said resistive reference element corresponds to a first logic state and a discharge current observed through said resistive change element lower than a discharge current through said resistive reference element corresponds to a second logic state.

4. The method of claim 1 wherein said resistive change elements are two-terminal nanotube switching elements.

5. The method of claim 4 wherein said two-terminal nanotube switching elements comprise a nanotube fabric.

6. The method of claim 1 wherein said resistive change elements are metal oxide memory elements.

7. The method of claim 1 wherein said resistive change elements are phase change memory elements.

8. The method of claim 1 wherein said resistive change element array is a memory array.

9. A method for adjusting the resistive state of at least one resistive change element within a resistive change element array, comprising:

providing a resistive change element array, said resistive change element array comprising;

a plurality of word lines;

a plurality of bit lines; and

a plurality of resistive change elements, wherein each resistive change element has a first terminal and a second terminal and wherein said first terminal of each resistive change element is in electrical communication with a word line and said second terminal of each resistive change element is in electrical communication with a bit line;

initializing all of said bit lines and all of said word lines within said resistive change element array to a ground;

selecting one word line, wherein said selected word line is in electrical communication with at least one resistive change element to be adjusted;

floating all of said word lines that are not selected;

pulling all of said bit lines to ground through selectable current limiting elements, wherein each of said selectable current limiting elements can be configured in at least two states, wherein a first configured state permits a sufficient programming current to flow through a selectable current limiting element and a second configured state inhibits a sufficient programming current from flowing through a selectable current limiting element;

configuring those selectable current limiting elements associated with those bit lines in electrical communication with a resistive change element to be adjusted into said first configured state and configuring those selectable current limiting elements associated with those bit lines in electrical communication with a resistive change element not to be adjusted into said second configured state;

driving said selected word line to a preselected voltage;

discharging said selected word line through at least one resistive change element to provide at least one programming current through at least one resistive change element;

wherein said at least one programming current adjusts the electrical resistance of at least one resistive change element from a first resistive state to a second resistive state.

10. The method of claim 9 wherein said selectable current limiting elements are one of current sources, adjustable resistive elements, or programmable power supplies.

11. The method of claim 9 wherein said first resistive state is lower than said second resistive state.

12. The method of claim 9 wherein said first resistive state is higher than said second resistive state.

13. The method of claim 9 wherein the resistive state of every resistive change element in electrical communication with said selected word line is adjusted simultaneously.

14. The method of claim 9 wherein said first resistive state corresponds to a first logic value and said second logic state corresponds to a second logic value.

15. The method of claim 14 wherein all the resistive change elements in electrical communication with said selected word line are programmed with the same logic value after said selected word line has discharged.

16. The method of claim 9 wherein said resistive change elements are two-terminal nanotube switching elements.

17. The method of claim 16 wherein said two-terminal nanotube switching elements comprise a nanotube fabric.

18. The method of claim 9 wherein said resistive change elements are metal oxide memory elements.

19. The method of claim 9 wherein said resistive change elements are phase change memory elements.

20. The method of claim 9 wherein said resistive change element array is a memory array.