Structure and method for advanced bulk fin isolation

• US 9,299,618 B1
• Filed: 09/24/2014
• Issued: 03/29/2016
• Est. Priority Date: 09/24/2014
• Status: Active Grant

• Current Assignee: Elpis Technologies Inc. (Wi-LAN Inc.)
• Original Assignee: International Business Machines Corporation
• Inventors: Cheng, Kangguo, Doris, Bruce B., Khakifirooz, Ali, Lu, Darsen D., Reznicek, Alexander, Rim, Kern
• Primary Examiner(s): HOANG, QUOC DINH
• Application Number:
  US14/495,342
• Publication Number:
  US 20160086858A1
• Time in Patent Office: 552 Days
• Field of Search: 438/283, 257/347
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02381 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/3081 characterised by their composition, e.g. multilayer masks, materials
• CPC Class Codes: H01L 21/823807 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823821 with a particular manufacturing method of transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/0924 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 29/1054 with a variation of the composition, e.g. channel with strained layer for increasing the mobility
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/165 in different semiconductor regions , e.g. heterojunctions

Abstract

A non-planar semiconductor structure containing semiconductor fins that are isolated from an underlying bulk silicon substrate by an epitaxial semiconductor stack is provided. The epitaxial semiconductor material stack that provides the isolation includes, from bottom to top, a semiconductor punch through stop containing at least one dopant of a conductivity type which differs from the conductivity type of the particular device region that the semiconductor fin is formed in, and a semiconductor diffusion barrier layer containing no n- or p-type dopant.

Claims

1. A method of forming a semiconductor structure, said method comprising:

providing a bulk silicon substrate comprising a first device region for a first semiconductor device of a first conductivity type and an adjacent second device region for a second semiconductor device of a second conductivity type;

recessing an exposed portion of said bulk silicon substrate in said first device region to expose a sub-surface of said bulk silicon substrate, wherein a hard mask layer portion is present on said second device region during said recessing;

forming a first semiconductor material stack of, from bottom to top, a semiconductor punch through stop layer comprising a first carbon-doped silicon layer containing at least one dopant of said second conductivity type which is opposite from said first conductivity type, a semiconductor diffusion barrier layer comprising a second carbon-doped silicon layer containing no n- or p-type dopant, and an epitaxial semiconductor layer comprising silicon or a silicon germanium alloy on said sub-surface of said bulk silicon substrate and in said first device region;

removing said hard mask layer portion in said second device region;

recessing said bulk silicon substrate in said second device region to expose another sub-surface of said bulk silicon substrate in said second device region;

forming a second semiconductor material stack on said another sub-surface of said bulk silicon substrate and in said second device region, wherein said second semiconductor material stack comprises, from bottom to top, a first silicon germanium alloy layer containing at least one dopant of said first conductivity type, a second silicon germanium alloy er containing no further dopant, and another epitaxial semiconductor layer; and

forming a plurality of first semiconductor fins in said first device region and a plurality of second semiconductor fins in said second device region, wherein each first semiconductor fin of said plurality of first semiconductor fins comprises, from bottom to top, a remaining portion of said semiconductor punch through stop layer, a remaining portion of said semiconductor diffusion barrier, and a remaining portion of said epitaxial semiconductor layer.

2. The method of claim 1, wherein each of said second semiconductor fins of said plurality of second semiconductor fins comprises from bottom to top, a remaining portion of said first silicon germanium alloy layer, a remaining portion of said second silicon germanium alloy layer, and a remaining portion of said another epitaxial semiconductor layer.

3. The method of claim 1, wherein said first device region is a pFET device region and said second device region is an nFET device region.

4. The method of claim 1, wherein said recessing said exposed portion of said bulk silicon substrate in said first device region comprises an anisotropic etch.

5. The method of claim 1, further comprising forming a dielectric spacer having a base located on said sub-surface of said bulk silicon substrate in said first device region prior to recessing said second device region.

6. The method of claim 5, wherein said forming said plurality of first semiconductor fins in said first device region and said plurality of second semiconductor fins in said second device region comprises a patterning process.

7. The method of claim 6, wherein said dielectric spacer is removed during said patterning.

8. The method of claim 7, wherein a recessed area is present in a remaining portion of said bulk silicon substrate.

9. The method of claim 1, further comprising forming a functional gate structure straddling over a portion of each first semiconductor fin of said plurality of first semiconductor fins and straddling over a portion of each second semiconductor fin of said plurality of second semiconductor fins.

10. A semiconductor structure comprising:

a bulk silicon substrate portion comprising a first device region for a semiconductor device of a first conductivity type and a second device region located adjacent to said first device region, wherein said second device region is for second semiconductor device having said second conductivity type;

a plurality of first semiconductor fins in said first device region and extending upward from said bulk silicon substrate portion, wherein each first semiconductor fin of said plurality of first semiconductor fins comprises, from bottom to top, a semiconductor punch through stop portion comprising a first carbon-doped silicon portion containing a dopant of the second conductivity type that is opposite from said first conductivity type, a semiconductor diffusion barrier portion comprising a second carbon-doped silicon portion containing no n- or p-type dopant, and an epitaxial semiconductor portion comprises silicon or a silicon germanium alloy; and

a plurality of second semiconductor fins in said second device region, wherein each second semiconductor fin of said plurality of second semiconductor fins comprises, from bottom to top, a first silicon germanium alloy portion containing a dopant of the first conductivity type that is opposite from said second conductivity type, a second silicon germanium alloy portion containing no further dopant, and another epitaxial semiconductor portion and extending upward from another sub-surface of said bulk silicon substrate portion.

11. The semiconductor structure of claim 10, wherein said another epitaxial semiconductor portion comprises silicon.

12. The semiconductor structure of claim 10, wherein said first device region is a pFET device region and said second device region is an nFET device region.

13. The semiconductor structure of claim 10, wherein said bulk silicon substrate portion contains a recessed area between said first device region and said second device region.

14. The semiconductor structure of claim 10, further comprising a functional gate structure straddling over a portion of each first semiconductor fin of said plurality of first semiconductor fins and straddling over a portion of each second semiconductor fin of said plurality of second semiconductor fins.

15. The semiconductor structure of claim 10, wherein said plurality of said first semiconductor fins has a same height as said plurality of said second semiconductor fins.