Semiconductor system, device and structure with heat removal

• US 9,299,641 B2
• Filed: 06/23/2015
• Issued: 03/29/2016
• Est. Priority Date: 08/10/2012
• Status: Active Grant

• Current Assignee: Monolithic 3D, Inc.
• Original Assignee: Monolithic 3D, Inc.
• Inventors: Sekar, Deepak, Or-Bach, Zvi, Cronquist, Brian
• Primary Examiner(s): NGUYEN, CUONG QUANG
• Application Number:
  US14/747,599
• Publication Number:
  US 20150311142A1
• Time in Patent Office: 280 Days
• Field of Search: 257/347, 257/758, 257/686, 257/712
• US Class Current: 1/1
• CPC Class Codes: H01L 21/823475 interconnection or wiring or contact manufacturing related aspects
• CPC Class Codes: H01L 2225/06527 Special adaptation of electrical connections, e.g. rewiring, engineering changes, pressure contacts, layout
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 2225/06589 Thermal management, e.g. cooling
• CPC Class Codes: H01L 23/3677 Wire-like or pin-like cooling fins or heat sinks
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 23/5225 Shielding layers formed together with wiring layers
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 27/0688 Integrated circuits having a three-dimensional layout
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 27/0886 including transistors with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A 3D device including: a first layer including first transistors, the first layer overlaid by at least one interconnection layer; a second layer including second transistors, the second layer overlaying the interconnection layer; a plurality of electrical connections connecting the second transistors with the interconnection layer; and at least one thermally conductive and electrically non-conductive contact, where the at least one thermally conductive and electrically non-conductive contact thermally connects the second layer to a top or bottom surface of the 3D device.

Claims

1. A 3D device comprising:

a first layer comprising first transistors, said first layer overlaid by at least one interconnection layer;

a second layer comprising second transistors, said second layer overlaying said interconnection layer;

a plurality of electrical connections connecting said second transistors with said interconnection layer; and

at least one thermally conductive and electrically non-conductive contact,

wherein said at least one thermally conductive and electrically non-conductive contact thermally connects said second layer to a top or bottom surface of said 3D device.

2. A 3D device according to claim 1,

wherein said plurality of electrical connections comprises at least one through-silicon-via, said at least one through-silicon-via comprises a material which has a thermal conductivity greater than 10 W/m-K.

3. A 3D device according to claim 1, further comprising:

a heat-spreader layer disposed between said first layer and said second layer.

4. A 3D device according to claim 1, further comprising:

a power distribution network to provide power to said second transistors,

wherein said power distribution network provides a heat removal path between at least one of said second transistors and the top or bottom surface of said 3D device.

5. A 3D device according to claim 1,

wherein said plurality of electrical connections comprise thru layer vias and,

wherein said thru layer vias have a density greater than 10,000 vias/cm².

6. A 3D device according to claim 1, further comprising:

a via through said second layer,

wherein said via is part of a heat removal structure of said device.

7. A 3D device according to claim 1,

wherein said interconnection layer comprises a power grid to provide power to at least one of said second transistors.

8. A system, comprising:

a 3D device, said 3D device comprising;

a first layer comprising first transistors, said first layer overlaid by a first interconnection layer;

a second layer comprising second transistors, said second layer overlaying said first interconnection layer;

a plurality of second interconnection layers overlaying said second layer;

a plurality of electrical connections connecting at least one of said second interconnection layers with said first interconnection layer; and

a plurality of thermally conducting paths from said second transistors to a top or bottom surface of said 3D device.

9. A system according to claim 8,

wherein said second layer has a thickness less than 2 microns.

10. A system according to claim 8, further comprising:

a heat-spreader layer disposed between said first layer and said second layer.

11. A system according to claim 8, further comprising:

a power distribution network to provide power to said second transistors,

wherein said power distribution network provides a heat removal path between at least one of said second transistors and the top or bottom surface of said 3D device.

12. A system according to claim 8,

wherein said plurality of electrical connections comprise thru layer vias and,

wherein said thru layer vias have a density greater than 10,000 vias/cm².

13. A system according to claim 8, further comprising:

at least one thermally conductive and electrically non-conducting contact to said second layer.

14. A system, comprising:

a 3D device, said 3D device comprising;

a first layer comprising first transistors, said first layer overlaid by at least one interconnection layer,

a second layer comprising second transistors, said second layer overlaying said interconnection layer;

a plurality of electrical connections connecting said second transistors with said interconnection layer;

said plurality of electrical connections further comprising;

a power distribution grid providing power to said second transistors, and

a plurality of thermally conducting paths from said power distribution grid to a top or bottom surface of said 3D device,

wherein said second layer has a thickness less than 2 microns.

15. A system according to claim 14,

wherein said plurality of electrical connections comprises a through-silicon connection, and

wherein at least one of said plurality of electrical connections comprises at least one thermally conductive and electrically non-conductive contact.

16. A system according to claim 14, further comprising:

a heat-spreader layer disposed between said first layer and said second layer.

17. A system according to claim 14,

wherein a portion of said power distribution grid is between said first layer and said second layer.

18. A system according to claim 14,

wherein said plurality of electrical connections comprise thru layer vias and,

wherein said thru layer vias have a density greater than 10,000 vias/cm².

19. A system according to claim 14, further comprising:

at least one thermally conductive and electrically non-conducting contact to said second layer.

20. A system according to claim 14,

wherein said second transistors are FinFET type transistors.