Semiconductor structure with multiple transistors having various threshold voltages

• US 9,299,698 B2
• Filed: 06/25/2013
• Issued: 03/29/2016
• Est. Priority Date: 06/27/2012
• Status: Active Grant

• Current Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Original Assignee: Mie Fujitsu Semiconductor Ltd (United Microelectronics Corporation)
• Inventors: Zhao, Dalong, Bakhishev, Teymur, Scudder, Lance, Gregory, Paul E., Duane, Michael, Sridharan, U. C., Ranade, Pushkar, Shifren, Lucian, Hoffmann, Thomas
• Primary Examiner(s): Jackson, Jr., Jerome
• Assistant Examiner(s): BUDD, PAUL A
• Application Number:
  US13/926,555
• Publication Number:
  US 20140001571A1
• Time in Patent Office: 1,008 Days
• Field of Search: 257/345
• US Class Current: 1/1
• CPC Class Codes: H01L 21/265 producing ion implantation
• CPC Class Codes: H01L 21/283 Deposition of conductive or insulating materials for electrodes conducting electric current
• CPC Class Codes: H01L 21/823412 with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
• CPC Class Codes: H01L 21/823493 with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
• CPC Class Codes: H01L 27/088 the components being field-effect transistors with insulated gate
• CPC Class Codes: H01L 29/105 with vertical doping variation H01L29/7827 takes precedence
• CPC Class Codes: H01L 29/1083 with an inactive supplementary region, e.g. for preventing punch-through, improving capacity effect or leakage current
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET
• CPC Class Codes: H01L 29/66537 using a self aligned punch through stopper or threshold implant under the gate region H01L29/66606 takes precedence
• CPC Class Codes: H01L 29/7833 with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's for thin film transistors H01L29/78618

Abstract

A semiconductor structure includes first, second, and third transistor elements each having a first screening region concurrently formed therein. A second screening region is formed in the second and third transistor elements such that there is at least one characteristic of the screening region in the second transistor element that is different than the second screening region in the third transistor element. Different characteristics include doping concentration and depth of implant. In addition, a different characteristic may be achieved by concurrently implanting the second screening region in the second and third transistor element followed by implanting an additional dopant into the second screening region of the third transistor element.

Claims

1. A semiconductor integrated circuit having a plurality of transistor devices fabricated on a substrate surface to support a plurality of threshold voltages, the transistor devices each having a gate with a source and a drain on either side of the gate, comprising:

a first transistor device region having a first screening region with a first preselected doping concentration and first thickness and set to be a first predefined depth below the substrate surface;

a second transistor device region having a second screening region with a second doping concentration and second thickness and second depth, wherein the second thickness and second depth are substantially similar to the first screening region but the second doping concentration is higher than the first doping concentration; and

a third transistor device region having a third screening region with a third doping concentration and third thickness and third depth, wherein the third thickness and third depth are substantially similar to the second screening region but the third doping concentration is higher than the second doping concentration;

wherein each of the first, second, and third screening regions are covered by a substantially undoped layer to form a channel;

wherein each of the first, second, and third screening regions extend laterally across the length of the channel and abut the source and drain;

wherein each of the first, second, and third screening regions are located to be below the surface of the substrate at a distance of at least less than 1/1.5 times a length of the gate and above the bottom of the source and drain to which each of the screening regions abuts;

wherein each of the first, second, and third transistor device regions each include a first antipunchthrough region underlying each respective screening region; and

wherein at least one of the first, second, and third transistor device regions includes a second antipunchthrough region underlying the first antipunchthrough region.

2. The semiconductor structure of claim 1, wherein the second transistor device region further includes a fourth screening region adjacent to the second screening region to form a dual screening structure.

3. The semiconductor structure of claim 2, wherein the second screening region is in contact with the fourth screening region.

4. The semiconductor structure of claim 1, wherein the third transistor device region further includes a fifth screening region adjacent to the third screening region to form a dual screening structure.

5. The semiconductor structure of claim 1, wherein the first antipunchthrough region is in contact with the second antipunchthrough region.

6. The semiconductor structure of claim 1, wherein the first antipunchthrough region is in contact with the first screening region of at least one of the first, second, and third transistor device regions.

7. The semiconductor structure of claim 1, wherein the substantially undoped layer comprises a blanket epitaxial layer.

8. The semiconductor structure of claim 7, wherein at least one of the first, second, and third transistor device regions includes a channel that includes stress in a channel crystalline structure.

9. A semiconductor integrated circuit having a transistor device fabricated on a substrate surface to support a threshold voltage, the transistor device having a gate with a source and a drain on either side of the gate, comprising a transistor device region having;

a screening region with a first doping concentration, located to be below the surface of the substrate at a distance of at least less than 1/1.5 times a length of the gate and above a bottom of the source and drain to which the screening region abuts;

a substantially undoped channel over the screening region;

a first antipunchthrough region with a second doping concentration less than the first doping concentration, underlying the screening region;

a second antipunchthrough region with a third doping concentration less than the first doping concentration, underlying the first antipunchthrough region.