Semiconductor device and method for fabricating the same

• US 9,299,704 B2
• Filed: 09/17/2014
• Issued: 03/29/2016
• Est. Priority Date: 06/26/2014
• Status: Active Grant

• Current Assignee: SK Hynix Inc.
• Original Assignee: SK Hynix Inc.
• Inventors: Ji, Yun-Hyuck, Joo, Moon-Sig, Jang, Se-Aug, Kim, Hyung-Chul
• Primary Examiner(s): Nguyen, Cuong Q
• Assistant Examiner(s): Kim, Tong-Ho
• Application Number:
  US14/489,237
• Publication Number:
  US 20150380407A1
• Time in Patent Office: 559 Days
• Field of Search: 257/211, 257/410, 257/369, 438/591, 438/592
• US Class Current: 1/1
• CPC Class Codes: H01L 21/02186 the material containing titanium, e.g. TiO2
• CPC Class Codes: H01L 21/02192 the material containing at least one rare earth metal element, e.g. oxides of lanthanides, scandium or yttrium
• CPC Class Codes: H01L 21/28088 the final conductor layer next to the insulator being a composite, e.g. TiN
• CPC Class Codes: H01L 21/28568 the conductive layers comprising transition metals H01L21/28518 takes precedence
• CPC Class Codes: H01L 21/31111 by chemical means
• CPC Class Codes: H01L 21/32139 using masks
• CPC Class Codes: H01L 21/823828 with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
• CPC Class Codes: H01L 21/823842 gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
• CPC Class Codes: H01L 27/092 complementary MIS field-effect transistors
• CPC Class Codes: H01L 27/0922 Combination of complementary transistors having a different structure, e.g. stacked CMOS, high-voltage and low-voltage CMOS
• CPC Class Codes: H01L 29/4966 the conductor material next to the insulator being a composite material, e.g. organic material, TiN, MoSi2 H01L29/4908, H01L29/4983 take precedence
• CPC Class Codes: H01L 29/513 the variation being perpendicular to the channel plane
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/665 using self aligned silicidation, i.e. salicide formation of conductive layers comprising silicides H01L21/28518
• CPC Class Codes: H01L 29/66545 using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate

Abstract

A method for fabricating a semiconductor device includes: forming a gate dielectric layer over a substrate; forming an etch stop layer over the gate dielectric layer; forming a first work function layer that covers a first portion of the etch stop layer and a sacrificial compound that covers a second portion of the etch stop layer; exposing the second portion of the etch stop layer by removing the sacrificial compound; and forming a second work function layer over the second portion of the etch stop layer and the first work function layer.

Claims

1. A method for fabricating a semiconductor device comprising:

forming a gate dielectric layer over a substrate;

forming an etch stop layer over the gate dielectric layer;

forming a sacrificial layer pattern over a second portion of the etch stop layer;

forming a first work function layer that covers a first portion of the etch stop layer and a sacrificial compound that covers the second portion of the etch stop layer;

exposing the second portion of the etch stop layer by removing the sacrificial compound; and

forming a second work function layer over the second portion of the etch stop layer and the first work function layer,

wherein the sacrificial compound is formed by a reaction between the sacrificial layer pattern and the first work function layer.

2. The method of claim 1, wherein the forming of the first work function layer that covers the first portion of the etch stop layer and the sacrificial compound that covers the second portion of the etch stop layer includes:

forming a sacrificial layer over the etch stop layer;

removing the sacrificial layer over the first portion of the etch stop layer to form a sacrificial layer pattern over the second portion of the etch stop layer; and

forming the first work function layer over the sacrificial layer pattern and the first portion of the etch stop layer,

wherein the sacrificial layer pattern is transformed into the sacrificial compound while the first work function layer is formed over the first portion of the etch stop layer.

3. The method of claim 2, wherein the sacrificial layer includes lanthanum oxide, and the sacrificial compound includes lanthanum chloride.

4. The method of claim 3, wherein the first work function layer includes titanium nitride,

wherein the first work function layer is formed by using titanium tetrachloride (TiCl₄).

5. The method of claim 1, wherein the first work function layer includes a titanium layer containing a first species, wherein the second work function layer includes a titanium layer containing a second species, and

wherein the second work function layer and the first work function layer have different work functions.

6. The method of claim 5, wherein the first species includes nitrogen, and the second species includes aluminum, carbon, or a combination thereof.

7. The method of claim 1, wherein the etch stop layer includes tantalum nitride.

8. The method of claim 1, further comprising:

forming a capping layer over the gate dielectric layer, before the forming of the etch stop layer,

wherein the capping layer includes titanium nitride.

9. A method for fabricating a semiconductor device, comprising:

preparing a substrate including a first channel region and a second channel region;

forming an inter-layer dielectric layer over the substrate, wherein the inter-layer dielectric layer includes a first trench exposing the first channel region and a second trench exposing the second channel region;

forming a gate dielectric layer in the first trench and the second trench;

forming an etch stop layer over the gate dielectric layer;

forming a sacrificial layer pattern over the etch stop layer in the second trench;

forming a first work function layer over the etch stop layer in the first trench and forming a sacrificial compound over the etch stop layer in the second trench;

exposing the etch stop layer in the second trench by removing the sacrificial compound;

forming a second work function layer over the first work function layer in the first trench and over the etch stop layer in the second trench; and

forming a low resistivity layer over the second work function layer to fill the first trench and the second trench,

wherein the sacrificial compound is formed by a reaction between the sacrificial layer pattern and the first work function layer.

10. The method of claim 9, wherein the forming of the first work function layer over the etch stop layer in the first trench and forming of the sacrificial compound over the etch stop layer in the second trench includes:

forming a sacrificial layer over the etch stop layer;

removing the sacrificial layer over the etch stop layer in the first trench to form a sacrificial layer pattern over the etch stop layer in the second trench; and

applying first work function material to the first and the second trenches to form the first work function layer over the etch stop layer in the first trench and to transform the sacrificial layer pattern in the second trench into the sacrificial compound.

11. The method of claim 10, wherein the sacrificial layer includes lanthanum oxide, and the sacrificial compound includes lanthanum chloride.

12. The method of claim 11, wherein the first work function layer includes titanium nitride, and

wherein the first work function material includes titanium tetrachloride (TiCl₄).

13. The method of claim 9, wherein the first work function layer includes titanium nitride, and

wherein the second work function layer includes a titanium layer containing a second species, and

wherein the second species is suitable to make the second work function layer and the first work function layer have different work functions.

14. The method of claim 13, wherein the species includes aluminum, carbon, or a combination thereof.

15. The method of claim 9, further comprising:

forming a capping layer over the gate dielectric layer, before the forming of the etch stop layer,

wherein the capping layer includes titanium nitride.

16. The method of claim 9, wherein the etch stop layer includes tantalum nitride.

17. The method of claim 9, wherein the first work function layer is suitable to serve as a P-channel transistor, and the second work function layer is suitable to serve as an N-channel transistor.